SN65LVDS390 四路 LVDS 接收器
This family of four-, eight-, or sixteen-, differential line receivers (with optional integrated termination) implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Any of the eight or sixteen differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals almost always requires the use of a line impedance matching resistor at the receiving end of the cable or transmission media.
| SN55LVDS31 | SN65LVDM31 | SN65LVDS047 | SN65LVDS048A | SN65LVDS31 | SN65LVDS32 | SN65LVDS33 | SN65LVDS348 | SN65LVDS352 | SN65LVDS390 | SN65LVDS391 | SN75LVDS31 | |
| Input Signal | LVTTL | LVCMOS | LVTTL | LVDS | LVTTL | LVDS | CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL | CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL | CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL | LVDS | LVTTL | |
| Output Signal | LVDS | LVDM | LVDS | LVTTL | LVDS | LVTTL | LVTTL | LVTTL | LVTTL | LVTTL | LVDS | LVTTL |
| No. of Rx | 4 | 4 | 4 | 4 | 4 | 4 | ||||||
| No. of Tx | 4 | 4 | 4 | 4 | 4 | 4 | 4 | |||||
| Signaling Rate(Mbps) | 400 | 150 | 400 | 400 | 400 | 100 | 400 | 340 | 560 | 630 | 630 | 155 |
| Supply Voltage(s)(V) | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 |
| ICC(Max)(mA) | 35 | 40 | 26 | 15 | 35 | 18 | 23 | 20 | 20 | 18 | 26 | 35 |
| Rx tpd(Typ)(ns) | 2.9 | 2.3 | 4 | 4 | 4 | 2.6 | ||||||
| Tx tpd(Typ)(ns) | 1.7 | 2.3 | 1.8 | 1.7 | 1.7 | |||||||
| Part-to-Part Skew(Max)(ps) | 1000 | 1000 | 1000 | 800 | 1000 | 1000 | 1000 | 1000 | 1500 | 1000 | ||
| Pin/Package | 16CDIP, 16CFP, 20LCCC | 16SOIC | 16SOIC, 16TSSOP | 16SOIC, 16TSSOP | 16SO, 16SOIC, 16TSSOP | 16SO, 16SOIC, 16TSSOP | 16SOIC, 16TSSOP | 16SOIC, 16TSSOP | 24TSSOP | 16SOIC, 16TSSOP | 16SOIC, 16TSSOP | 16SOIC, 16TSSOP |
| Operating Temperature Range(°C) | -55 to 125 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | 0 to 70 |
| ESD HBM(kV) | 8 | 12 | 8 | 10 | 8 | 8 | 15 | 15 | 15 | 15 | ||
| Approx. Price (US$) | 1.50 | 1ku | 1.85 | 1ku | 1.30 | 1ku | 1.30 | 1ku | 1.30 | 1ku | 1.20 | 1ku | 1.65 | 1ku | 2.90 | 1ku | 1.20 | 1ku | 1.20 | 1ku | 1.30 | 1ku |
SN65LVDS390 特性
- Four- ('390), Eight- ('388A), or Sixteen- ('386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
- Integrated 110-
Line Termination Resistors on LVDT Products
- Designed for Signaling Rates(1) Up To 200 Mbps
- SN65 Version's Bus-Terminal ESD Exceeds 15 kV
- Operates From a Single 3.3-V Supply
- Typical Propagation Delay Time of 2.6 ns
- Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns
- LVTTL Levels Are 5-V Tolerant
- Open-Circuit FailSafe
- Flow-Through Pinout
- Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch
SN65LVDS390 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN65LVDS390D | ACTIVE | -40 to 85 | 1.55 | 1ku | SOIC (D) | 16 | 40 | TUBE | |
| SN65LVDS390DG4 | ACTIVE | -40 to 85 | 1.55 | 1ku | SOIC (D) | 16 | 40 | TUBE | |
| SN65LVDS390DR | ACTIVE | -40 to 85 | 1.30 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | |
| SN65LVDS390DRG4 | ACTIVE | -40 to 85 | 1.30 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | |
| SN65LVDS390PW | ACTIVE | -40 to 85 | 1.55 | 1ku | TSSOP (PW) | 16 | 90 | TUBE | |
| SN65LVDS390PWG4 | ACTIVE | -40 to 85 | 1.55 | 1ku | TSSOP (PW) | 16 | 90 | TUBE | |
| SN65LVDS390PWR | ACTIVE | -40 to 85 | 1.30 | 1ku | TSSOP (PW) | 16 | 2000 | LARGE T&R | |
| SN65LVDS390PWRG4 | ACTIVE | -40 to 85 | 1.30 | 1ku | TSSOP (PW) | 16 | 2000 | LARGE T&R |
SN65LVDS390 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN65LVDS390D | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS390D | SN65LVDS390D |
| SN65LVDS390DG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS390DG4 | SN65LVDS390DG4 |
| SN65LVDS390DR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS390DR | SN65LVDS390DR |
| SN65LVDS390DRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS390DRG4 | SN65LVDS390DRG4 |
| SN65LVDS390PW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS390PW | SN65LVDS390PW |
| SN65LVDS390PWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS390PWG4 | SN65LVDS390PWG4 |
| SN65LVDS390PWR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS390PWR | SN65LVDS390PWR |
| SN65LVDS390PWRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS390PWRG4 | SN65LVDS390PWRG4 |
SN65LVDS390 应用技术支持与电子电路设计开发资源下载
- SN65LVDS390 数据资料 dataSheet 下载.PDF
- TI 德州仪器LVDS PHYs选型与价格 . xls
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
- 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
- 接口选择指南 (Rev. D) (PDF 2994 KB)
- Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
- Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
- Isolated RS-485 Reference Design (PDF 80 KB)
- 无铅组件涂层的保存期评估 (PDF 1305 KB)
- Analog Signal Chain Guide (8.62 MB)
- Industrial Interface IC Solutions (101 KB)