SN65LVDM051 双路 LVDS 发送器/接收器
The intended application of these devices and signaling techniques is point-to-point half duplex, baseband data transmission over a controlled impedance media of approximately 100
SN65LVDM050 SN65LVDM051 SN65LVDS049 SN65LVDS050 SN65LVDS051 SN65LVDS1050 SN65LVDS32B SN65LVDS33 SN65LVDT32B SN65LVDT33
No. of Rx
2
2
2
2
2
2
4
4
4
4
No. of Tx
2
2
2
2
2
2
Input Signal
LVDM, LVTTL
LVDM, LVTTL
LVDS, LVTTL
LVDS, LVTTL
LVDS, LVTTL
LVDS, LVTTL
LVDS
CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL
LVDS
LVDS, LVECL, LVPECL, PECL
Output Signal
LVDM, LVTTL
LVDM, LVTTL
LVDS, LVTTL
LVDS, LVTTL
LVDS, LVTTL
LVDS, LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Signaling Rate(Mbps)
500TX/100RX
500TX/100RX
400
400TX/100RX
400TX/100RX
400
400
400
400
400
Supply Voltage(s)(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
ICC(Max)(mA)
27
27
35
20
20
20
23
23
23
23
Part-to-Part Skew(Max)(ps)
1000
1000
1000
1000
1000
1000
1000
Rx tpd(Typ)(ns)
3.7
3.7
1.9
3.7
3.7
3.7
4
4
4
4
Tx tpd(Typ)(ns)
1.7
1.7
1.3
1.7
1.7
1.7
Pin/Package
16SOIC, 16TSSOP
16SOIC, 16TSSOP
16TSSOP
16SOIC, 16TSSOP
16SOIC, 16TSSOP
16TSSOP
16SOIC
16SOIC, 16TSSOP
16SOIC
16SOIC, 16TSSOP
Operating Temperature Range(C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
ESD HBM(kV)
12
12
10
12
12
12
15
15
15
15
SN65LVDM051 特性
Low-Voltage Differential 50- Typical Full-Duplex Signaling Rates of 100 Mbps
Bus-Terminal ESD Exceeds 12 kV
Operates From a Single 3.3-V Supply
Low-Voltage Differential Signaling With Typical
Output Voltages of 340 mV With a 50- Valid Output With as Little as 50-mV Input
Voltage Difference
Propagation Delay Times
Driver: 1.7 ns Typical
Receiver: 3.7 ns Typical
Power Dissipation at 200 MHz
Driver: 50 mW Typical
Receiver: 60 mW Typical
LVTTL Input Levels Are 5-V Tolerant
Driver Is High Impedance When Disabled or With VCC < 1.5 V
Receiver Has Open-Circuit Failsafe
SN65LVDM051 芯片订购指南
器件
状态
温度
价格
封装 | 引脚
封装数量 | 封装载体
丝印标记
SN65LVDM051D
ACTIVE
-40 to 85
1.80 | 1ku
SOIC (D) | 16 40 | TUBE
SN65LVDM051DG4
ACTIVE
-40 to 85
1.80 | 1ku
SOIC (D) | 16 40 | TUBE
SN65LVDM051DR
ACTIVE
-40 to 85
1.50 | 1ku
SOIC (D) | 16 2500 | LARGE T&R
SN65LVDM051DRG4
ACTIVE
-40 to 85
1.50 | 1ku
SOIC (D) | 16 2500 | LARGE T&R
SN65LVDM051PW
ACTIVE
-40 to 85
1.80 | 1ku
TSSOP (PW) | 16 90 | TUBE
SN65LVDM051PWG4
ACTIVE
-40 to 85
1.80 | 1ku
TSSOP (PW) | 16 90 | TUBE
SN65LVDM051PWR
ACTIVE
-40 to 85
1.50 | 1ku
TSSOP (PW) | 16 2000 | LARGE T&R
SN65LVDM051PWRG4
ACTIVE
-40 to 85
1.50 | 1ku
TSSOP (PW) | 16 2000 | LARGE T&R
SN65LVDM051 质量与无铅数据
器件
环保计划*
铅/焊球涂层
MSL 等级/回流焊峰
环保信息与无铅 (Pb-free)
DPPM / MTBF / FIT 率
SN65LVDM051D
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDM051D
SN65LVDM051D
SN65LVDM051DG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDM051DG4 SN65LVDM051DG4
SN65LVDM051DR
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDM051DR
SN65LVDM051DR
SN65LVDM051DRG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDM051DRG4 SN65LVDM051DRG4
SN65LVDM051PW
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDM051PW
SN65LVDM051PW
SN65LVDM051PWG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDM051PWG4 SN65LVDM051PWG4
SN65LVDM051PWR
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDM051PWR
SN65LVDM051PWR
SN65LVDM051PWRG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDM051PWRG4 SN65LVDM051PWRG4
SN65LVDM051 应用技术支持与电子电路设计开发资源下载
SN65LVDM051 数据资料 dataSheet 下载 .PDF TI 德州仪器M-LVDS PHYs选型与价格 . xls 所选封装材料的热学和电学性质 (PDF 645 KB)使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)接口选择指南 (Rev. D) (PDF 2994 KB)Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)Isolated RS-485 Reference Design (PDF 80 KB)无铅组件涂层的保存期评估 (PDF 1305 KB)Analog Signal Chain Guide (8.62 MB)Industrial Interface IC Solutions (101 KB)
The SN65LVDM179, SN65LVDM180, SN65LVDM050, and SN65LVDM051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve high signaling rates. These circuits are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts, except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV across a 50-
load simulating two transmission lines in parallel. This allows having data buses with more than one driver or with two line termination resistors. The receivers detect a voltage difference of 50 mV with up to 1 V of ground potential difference between a transmitter and receiver.