SN65LVDS18 具有使能端的 2.5V/3.3V 振荡器增益级/缓冲器
These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.
The SN65LVx18 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx19 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open
|
SN65CML100 |
SN65LVDS100 |
SN65LVDS101 |
SN65LVDS16 |
SN65LVDS17 |
SN65LVDS18 |
SN65LVDS19 |
SN65LVDS20 |
SN65LVP16 |
SN65LVP17 |
SN65LVP18 |
SN65LVP19 |
SN65LVP20 |
| Supply Voltage(s)(V) |
3.3 |
3.3 |
3.3 |
2.5 , 3.3 |
2.5 , 3.3 |
2.5 , 3.3 |
2.5 , 3.3 |
2.5 , 3.3 |
2.5 , 3.3 |
2.5 , 3.3 |
2.5 , 3.3 |
2.5 , 3.3 |
2.5 , 3.3 |
| ICC(Max)(mA) |
12 |
30 |
90 |
48 |
48 |
36 |
36 |
45 |
48 |
48 |
36 |
36 |
45 |
| Signaling Rate(Mbps) |
1500 |
2000 |
2000 |
4000 |
4000 |
2000 |
2000 |
4000 |
4000 |
4000 |
4000 |
2000 |
4000 |
| No. of Tx |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Operating Temperature Range(C) |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
| Tx tpd(Typ)(ns) |
|
|
|
0.460 |
0.460 |
0.460 |
0.460 |
0.450 |
0.460 |
0.460 |
0.460 |
0.460 |
0.450 |
| No. of Rx |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Input Signal |
CML, LVDS, LVPECL |
CML, LVDS, LVPECL |
CML, LVDS, LVPECL |
Single-Ended |
Differential |
Single-Ended |
Differential |
Differential |
Single-Ended |
Differential |
Single-Ended |
Differential |
Differential |
| Rx tpd(Typ)(ns) |
0.8 |
0.8 |
0.9 |
|
|
|
|
0.630 |
|
|
|
|
0.630 |
| Output Signal |
CML |
LVDS |
LVPECL |
LVDS |
LVDS |
LVDS |
LVDS |
LVDS |
LVPECL |
LVPECL |
LVPECL |
LVPECL |
LVPECL |
| Peak-to-Peak Jitter(Max)(ps) |
70 |
65 |
61 |
|
|
|
|
35 |
|
|
|
|
35 |
| Part-to-Part Skew(Max)(ps) |
100 |
100 |
100 |
80 |
80 |
80 |
80 |
80 |
80 |
80 |
80 |
80 |
80 |
| ESD HBM(kV) |
5 |
5 |
5 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
| Pin/Package |
8MSOP, 8SOIC |
8MSOP, 8SOIC |
8MSOP, 8SOIC |
8WSON |
8WSON |
8WSON |
8WSON |
8WSON |
8WSON |
8WSON |
8WSON |
8WSON |
8WSON |
SN65LVDS18 特性
- Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
- Clock Rates to 1 GHz
- 250-ps Output Transition Times
- 0.12 ps Typical Intrinsic Phase Jitter
- Less than 630 ps Propagation Delay Times
- 2.5-V or 3.3-V Supply Operation
- 2-mm x 2-mm Small-Outline No-Lead Package
- APPLICATIONS
- PECL-to-LVDS Translation
- Clock Signal Amplification
SN65LVDS18 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN65LVDS18DRFR |
ACTIVE |
-40 to 85 |
1.90 | 1ku |
WSON (DRF) | 8 |
3000 | LARGE T&R |
|
| SN65LVDS18DRFRG4 |
ACTIVE |
-40 to 85 |
1.90 | 1ku |
WSON (DRF) | 8 |
3000 | LARGE T&R |
|
| SN65LVDS18DRFT |
ACTIVE |
-40 to 85 |
2.20 | 1ku |
WSON (DRF) | 8 |
250 | SMALL T&R |
|
| SN65LVDS18DRFTG4 |
ACTIVE |
-40 to 85 |
2.20 | 1ku |
WSON (DRF) | 8 |
250 | SMALL T&R |
|
SN65LVDS18 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN65LVDS18DRFR |
Pb-Free (RoHS) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN65LVDS18DRFR |
SN65LVDS18DRFR |
| SN65LVDS18DRFRG4 |
Pb-Free (RoHS) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN65LVDS18DRFRG4 |
SN65LVDS18DRFRG4 |
| SN65LVDS18DRFT |
Pb-Free (RoHS) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN65LVDS18DRFT |
SN65LVDS18DRFT |
| SN65LVDS18DRFTG4 |
Pb-Free (RoHS) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN65LVDS18DRFTG4 |
SN65LVDS18DRFTG4 |
SN65LVDS18 应用技术支持与电子电路设计开发资源下载
- SN65LVDS18 数据资料 dataSheet 下载.PDF
- TI 德州仪器转发器/转换器选型与价格 . xls
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
- 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
- 接口选择指南 (Rev. D) (PDF 2994 KB)
- Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
- Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
- Isolated RS-485 Reference Design (PDF 80 KB)
- 无铅组件涂层的保存期评估 (PDF 1305 KB)
- Analog Signal Chain Guide (8.62 MB)
- Industrial Interface IC Solutions (101 KB)
SN65LVDS18 工具和软件