SN65LVDS116 1:8 LVDS 时钟扇出缓冲器 _ WOSENDONGLI代理SN65LVDS116

	SN65LVDS104	SN65LVDS105	SN65LVDS108	SN65LVDS116
Input Signal	315	315	311	311
Output Signal	3.3	3.3	3.3	3.3
No. of Rx	LVDS	LVTTL	LVDS	LVDS
No. of Tx	4	4	8	16
Operating Temperature Range(°C)	LVDS	LVDS	LVDS	LVDS
ESD HBM(kV)	16SOIC, 16TSSOP	16SOIC, 16TSSOP	38TSSOP	64TSSOP
Approx. Price (US$)	-40 to 85	-40 to 85	-40 to 85	-40 to 85

One Receiver and Sixteen Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
Enabling Logic Allows Separate Control of Each Bank of Four Channels or 2-Bit Selection of Any One of the Four Banks
Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100

SN65LVDS116 芯片订购指南

器件	状态	温度	价格	封装 \| 引脚	封装数量 \| 封装载体	丝印标记
SN65LVDS116DGG	ACTIVE	-40 to 85	5.40 \| 1ku	TSSOP (DGG) \| 64	25 \| TUBE
SN65LVDS116DGGG4	ACTIVE	-40 to 85	5.40 \| 1ku	TSSOP (DGG) \| 64	25 \| TUBE
SN65LVDS116DGGR	ACTIVE	-40 to 85	4.50 \| 1ku	TSSOP (DGG) \| 64	2000 \| LARGE T&R
SN65LVDS116DGGRG4	ACTIVE	-40 to 85	4.50 \| 1ku	TSSOP (DGG) \| 64	2000 \| LARGE T&R