SN65LVDS105 1 LVTTL:4 LVDS 时钟扇出缓冲器
The SN65LVDS104 and SN65LVDS105 are a differential line receiver and a LVTTL input (respectively) connected to four differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low-noise coupling, and switching speeds to transmit data at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
The SN65LVDS104 and SN65LVDS105 are characterized for operation from –40°C to 85°C.
The SN65LVDS104 and SN65LVDS105 are members of a family of LVDS repeaters
| SN65LVDS104 | SN65LVDS105 | SN65LVDS108 | SN65LVDS116 | |
| Input Signal | 315 | 315 | 311 | 311 |
| Output Signal | 3.3 | 3.3 | 3.3 | 3.3 |
| No. of Rx | LVDS | LVTTL | LVDS | LVDS |
| No. of Tx | 4 | 4 | 8 | 16 |
| Operating Temperature Range(°C) | LVDS | LVDS | LVDS | LVDS |
| ESD HBM(kV) | 16SOIC, 16TSSOP | 16SOIC, 16TSSOP | 38TSSOP | 64TSSOP |
| Approx. Price (US$) | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
SN65LVDS105 特性
- Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
- SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels
- SN65LVDS104 Receives Differential Input Levels, ±100 mV
- Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
- Operates From a Single 3.3-V Supply
- Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100
SN65LVDS105 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN65LVDS105D | ACTIVE | -40 to 85 | 2.35 | 1ku | SOIC (D) | 16 | 40 | TUBE | |
| SN65LVDS105DG4 | ACTIVE | -40 to 85 | 2.35 | 1ku | SOIC (D) | 16 | 40 | TUBE | |
| SN65LVDS105DR | ACTIVE | -40 to 85 | 1.95 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | |
| SN65LVDS105DRG4 | ACTIVE | -40 to 85 | 1.95 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | |
| SN65LVDS105PW | ACTIVE | -40 to 85 | 2.35 | 1ku | TSSOP (PW) | 16 | 90 | TUBE | |
| SN65LVDS105PWG4 | ACTIVE | -40 to 85 | 2.35 | 1ku | TSSOP (PW) | 16 | 90 | TUBE | |
| SN65LVDS105PWR | ACTIVE | -40 to 85 | 1.95 | 1ku | TSSOP (PW) | 16 | 2000 | LARGE T&R | |
| SN65LVDS105PWRG4 | ACTIVE | -40 to 85 | 1.95 | 1ku | TSSOP (PW) | 16 | 2000 | LARGE T&R |
SN65LVDS105 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN65LVDS105D | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS105D | SN65LVDS105D |
| SN65LVDS105DG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS105DG4 | SN65LVDS105DG4 |
| SN65LVDS105DR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS105DR | SN65LVDS105DR |
| SN65LVDS105DRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS105DRG4 | SN65LVDS105DRG4 |
| SN65LVDS105PW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS105PW | SN65LVDS105PW |
| SN65LVDS105PWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS105PWG4 | SN65LVDS105PWG4 |
| SN65LVDS105PWR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS105PWR | SN65LVDS105PWR |
| SN65LVDS105PWRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN65LVDS105PWRG4 | SN65LVDS105PWRG4 |
SN65LVDS105 应用技术支持与电子电路设计开发资源下载
- SN65LVDS105 数据资料 dataSheet 下载.PDF
- TI 德州仪器LVDS PHYs选型与价格 . xls
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
- 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
- 接口选择指南 (Rev. D) (PDF 2994 KB)
- Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
- Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
- Isolated RS-485 Reference Design (PDF 80 KB)
- 无铅组件涂层的保存期评估 (PDF 1305 KB)
- Analog Signal Chain Guide (8.62 MB)
- Industrial Interface IC Solutions (101 KB)