The M95256, M95256-W and M95256-R are electrically erasable programmable memory (EEPROM) devices. They are accessed by a high speed SPI-compatible bus. Their memory array is organized as 32768 x 8 bits.
The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 1. The device is selected when Chip Select (S) is taken low. Communications with the device can be interrupted using Hold (HOLD).
Ordering Model | Storage Capacity | Serial Interface | Marketing Status | Automotive Grade | Supply Voltage(Vcc) | Supply Voltage(Vcc) | Clock Frequency(fSCL) | Package |
spec | min | max | max | |||||
kB | V | V | MHz | |||||
M24256-BHR | 256 | I2C | Active | - | 1.8 | 5.5 | 1 | SO8; TSSOP8 |
M24256-BR | 256 | I2C | Active | - | 1.8 | 5.5 | 0.4 | SO8; TSSOP8; WLCSP-R |
M24256-BW | 256 | I2C | Active | - | 2.5 | 5.5 | 0.4 | SO 08 WIDE .208 (EIAJ); SO8; TSSOP8 |
M95256 | 256 | SPI | Active | Yes | 4.5 | 5.5 | 5 | SO8 |
M95256-R | 256 | SPI | Active | - | 1.8 | 5.5 | 2 | SO8; TSSOP8; WLCSP-R |
M95256-W | 256 | SPI | Active | Yes | 2.5 | 5.5 | 5 | SO 08 WIDE .208 (EIAJ); SO8; TSSOP8 |