AT89C51CC03 带有64K系统内可编程FLash存储器
| Flash (Kbytes) |
64 |
| CAN (mess. Obj.) |
15 |
| ISP |
Yes |
| Self Program Memory |
Yes |
| EEPROM (Kbytes) |
2 |
| RAM (Bytes) |
2304 |
| F.max (MHz) |
40 |
| Vcc (V) |
3-5.5 |
| I/O Pins |
34/37 |
| UART |
1 |
| 16-bit Timers |
2 |
| Watchdog |
Yes |
| SPI |
Yes |
| ADC |
Yes |
| Packages |
LQFP 64
LQFP 44
PLCC 52
PLCC 44 |
| Pb-Free Packages |
LQFP 64
LQFP 44
PLCC 52 |
AT89C51CC03 概述
The Atmel AT89C51CC03 is an 8051 based CMOS controller with PCA, Dual DPTR, WDT, 10 Bit ADC, Full CAN, 40 MHz High-Speed Architecture, X2 function, 32+2 I/O lines, 3 Timers/Counters, 14 Interrupts/4 priority levels, 64K FLASH, 2K EEPROM,256 Bytes on-chip RAM, additional 1K XRAM This document describes the UART bootloader functionalities as well as the serial protocol to efficiently perform operations on the on chip Flash (EEPROM) memories. Additiona l infor m ation on the AT89C51CC03 pr oduct c an be found in the AT89C51CC03 datasheet and the AT89C51CC03 errata sheet available on the Atmel web site.
AT89C51CC03 特性
- 80C51 Core Architecture
- 256 Bytes of On-chip RAM
- 2048 Bytes of On-chip ERAM
- 64K Bytes of On-chip Flash Memory
– Data Retention: 10 Years at 85°C
– Read/Write Cycle: 100K
- 2K Bytes of On-chip Flash for Bootloader
- 2K Bytes of On-chip EEPROM
Read/Write Cycle: 100K
- Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply
- 14-sources 4-level Interrupts
- Three 16-bit Timers/Counters
- Full Duplex UART Compatible 80C51
- High-speed Architecture
– In Standard Mode:
40 MHz (Vcc 3V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– In X2 mode (6 Clocks/machine cycle)
20 MHz (Vcc 3V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
- Five Ports: 32 + 4 Digital I/O Lines
- Five-channel 16-bit PCA with
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
- Double Data Pointer
- 21-bit WatchDog Timer (7 Programmable Bits)
- A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
- SPI Interface, (PLCC52 and VPFP64 packages only)
- Full CAN Controller
– Fully Compliant with CAN Rev 2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 15 Independent Message Objects
– Each Message Object Programmable on Transmission or Reception
– Individual Tag and Mask Filters up to 29-bit Identifier/Channel
– 8-byte Cyclic Data Register (FIFO)/Message Object
– 16-bit Status and Control Register/Message Object
– 16-bit Time-Stamping Register/Message Object
– CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object
– Access to Message Object Control and Data Registers Via SFR
– Programmable Reception Buffer Length Up To 15 Message Objects
– Priority Management of Reception of Hits on Several Message Objects at the
Same Time (Basic CAN Feature)
– Priority Management for Transmission
– Message Object Overrun Interrupt
– Supports
– Time Triggered Communication
– Autobaud and Listening Mode
– Programmable Automatic Reply Mode
– 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode
– Readable Error Counters
– Programmable Link to On-chip Timer for Time Stamping and Network
Synchronization
– Independent Baud Rate Prescaler
– Data, Remote, Error and Overload Frame Handling
AT89C51CC03 订购型号
AT89C51CC03 应用技术支持与电子电路设计开发资源下载
- AT89C51CC03 数据手册DataSheet 下载. PDF
- 80C51微控制器的复位输入. PDF (编号: Tech 8051 00049)
- 80C51在系统Flash编程. PDF (编号:8051 00050)