AD9889B: High Performance HDMITM/DVI Transmitter
The AD9889B is a 165 MHz, high definition multimedia inter-face (HDMITM) v. 1.3 transmitter. It supports HDTV formats up to 1080p, and computer graphic resolutions up to UXGA (1600 × 1200 @ 60 Hz). With the inclusion of HDCP, the AD9889B allows the secure transmission of protected content as specified by the HDCP v. 1.2 protocol.
The AD9889B supports both S/PDIF and 8-channel I2S audio. Its high fidelity, 8-channel I2S can transmit either stereo or 7.1 surround audio at 192 kHz. The S/PDIF can carry stereo LPCM audio or compressed audio, including DTS(R), THX(R), and Dolby(R) Digital.
The AD9889B helps reduce system design complexity and cost by incorporating such features as an internal MPU for HDCP operations, an I^2C master for EDID reading, a single 1.8 V power supply, and 5 V tolerance on the I^2C and hot plug detect pins.
Fabricated in an advanced CMOS process, the AD9889B is available in a space-saving, 76-ball CSP_BGA or 64-lead LFCSP surface-mount package, and an 80-lead LQFP surface-mount package. All packages are available as Pb-free and are specified from -25°C to +85°C.
产品应用领域 Applications
- DVD players and recorders
- Digital set-top boxes
- A/V receivers
- Digital cameras and camcorders
- HDMI repeater/splitter
AD9889B 特点
General
- HDMITM/DVI transmitter compatible with HDMI v. 1.3, DVI v. 1.0, and HDCP v. 1.2
- Single 1.8 V power supply
- Video/audio inputs accept logic levels from 1.8 V to 3.3 V
- 80-lead LQFP, Pb-free package
- 64-lead LFCSP, Pb-free package
- 76-ball CSP_BGA, Pb-free package
Digital video
- 165 MHz operation supports all resolutions from 480i to 1080p and UXGA at 60 Hz
- Programmable two-way color space converter
- Supports RGB, YCbCr, and DDR
- Supports ITU656-based embedded syncs
- Automatic input video format timing detection (CEA-861B)
Digital audio
- Supports standard S/PDIF for stereo LPCM or compressed audio up to 192 kHz
- 8-channel, uncompressed, LPCM I2S audio up to 192 kHz
Special features for easy system design
- On-chip MPU with I^2C(R) master to perform HDCP operations and EDID reading operations
- 5 V tolerant I^2C and HPD I/Os, no extra device needed
- No audio master clock needed for supporting S/PDIF and I2S
- On-chip MPU reports HDMI events through interrupts and registers
AD9889B功能框图
| 产品型号 | 产品状态 | 封装 | 引脚 | 温度范围 |
|---|---|---|---|---|
| AD9889B/PCBZ | 量产 | 评估板 | 80 | 商业 |
| AD9889BBBCZ-80 | 量产 | 76 ball CSPBGA (6x6x1.4mm) | 76 | 商业 |
| AD9889BBBCZRL-80 | 量产 | 76 ball CSPBGA (6x6x1.4mm) | 76 | 商业 |
| AD9889BBCPZ-165 | 量产 | 64 ld LFCSP (9x9mm, 4.70mm exposed pad) | 64 | 商业 |
| AD9889BBCPZ-80 | 量产 | 64 ld LFCSP (9x9mm, 4.70mm exposed pad) | 64 | 商业 |
| AD9889BBSTZ-165 | 量产 | 80 ld LQFP (14x14mm) | 80 | 商业 |
| AD9889BBSTZ-80 | 量产 | 80 ld LQFP (14x14mm) | 80 | 商业 |