AD9888KSZ-170: 205 MSPS Highly Integrated Graphics Digitizer for UXGA and HDTV Displays
The AD9888 is a complete 8-bit, 205 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 205 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports resolutions up to UXGA (1600 x 1200 at 75 Hz).
For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for FPDs. The AD9888 includes an analog interface with a 205 MHz triple ADC with internal +1.25 V reference, PLL to generate a pixel clock from Hsync and Coast, mid-scale clamping, and programmable gain, offset, and clamp control. The user provides only a +3.3 V power supply, analog input, and Hsync and Coast signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9888's on-chip PLL generates a pixel clock from Hsync and Coast inputs. Pixel clock output frequencies range from 10 to 205 MHz. PLL clock jitter is less than 500 ps p-p typical at 205 MSPS. When the Coast signal is presented, the PLL maintains its output frequency in the absence of Hsync. A sampling phase adjustment is provided. Data, Hsync and Clock output phase relationships are maintained. The PLL can be disabled and an external clock input provided as the pixel clock. The AD9888 also offers full sync processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This interface is fully programmable via a two wire serial interface.
Fabricated in an advanced CMOS process, the AD9888 is provided in a space-saving 128-lead MQFP surface mount plastic package and is specified over the 0°C to +70°C temperature range.
产品应用领域 Applications
- RGB Graphics Processing
- LCD Monitors and Projectors
- Plasma Display Panels
- Scan Converters
- Microdisplays
- Digital TV
AD9888KSZ-170 特点
- 205 MSPS Maximum Conversion Rate
- 500 MHz Programmable Analog Bandwidth
- 0.5 V to 1.0 V Analog Input Range
- Less than 450 ps p-p PLL Clock Jitter @ 205 MSPS
- 3.3 V Power Supply
- Full Sync Processing
- Sync Detect for "Hot Plugging"
- 2:1 Analog Input Mux
- 4:2:2 Output Format Mode
- Midscale Clamping
- Power-Down Mode
- Low Power: <1 W Typical @205 MSPS
AD9888KSZ-170 功能框图
| 产品型号 | 产品状态 | 封装 | 引脚 | 温度范围 |
|---|---|---|---|---|
| AD9888KSZ-100 | 量产 | 128 ld MQFP (14x20mm) | 128 | 商业 |
| AD9888KSZ-140 | 量产 | 128 ld MQFP (14x20mm) | 128 | 商业 |
| AD9888KSZ-170 | 量产 | 128 ld MQFP (14x20mm) | 128 | 商业 |
| AD9888KSZ-205 | 量产 | 128 ld MQFP (14x20mm) | 128 | 商业 |