SN74LS670 具有三态输出的 4 x 4 寄存器文件
The SN54LS670 and SN74LS670 MSI 16-bit TTL register files incorporate the equivalent of 98 gates. The register file is organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data. This permits simultaneous writing into one location and reading from another word location.
Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined by the write-address inputs A and B in conjunction with a write-enable signal. Data applied at the inputs should be in its true form. That is, if a high-level signal is desired from the output, a high-level is applied at the data input for that particular bit location
| SN74LS670 | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.75 to 5.25 |
| Input Level | TTL |
| Output Level | TTL |
| Output Drive(mA) | -2.6/8 |
| Output | 3S |
| No. of Bits | 16 |
| th(ns) | 5 |
| tpd max(ns) | 45 |
| tsu(ns) | 15 |
| Rating | Catalog |
| Technology Family | LS |
SN74LS670 特性
- Separate Read/Write Addressing Permits Simultaneous Reading and Writing
- Fast Access Times…Typically 20 ns
- Organized as 4 Words of 4 Bits
- Expandable to 512 Words of n-Bits
- For Use as:
- Scratch-Pad Memory
- Buffer Storage between Processors
- Bit Storage in Fast Multiplication Designs
- 3-State Outputs
- SN54LS170 and SN74LS170 Are Similar But Have Open-Collector Outputs
SN74LS670 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LS670D | ACTIVE | 0 to 70 | 2.70 | 1ku | SOIC (D) | 16 | 40 | TUBE | LS670 |
| SN74LS670DE4 | ACTIVE | 0 to 70 | 2.70 | 1ku | SOIC (D) | 16 | 40 | TUBE | LS670 |
| SN74LS670DG4 | ACTIVE | 0 to 70 | 2.70 | 1ku | SOIC (D) | 16 | 40 | TUBE | LS670 |
| SN74LS670DR | ACTIVE | 0 to 70 | 2.25 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | LS670 |
| SN74LS670DRE4 | ACTIVE | 0 to 70 | 2.25 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | LS670 |
| SN74LS670DRG4 | ACTIVE | 0 to 70 | 2.25 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | LS670 |
| SN74LS670N | ACTIVE | 0 to 70 | 2.45 | 1ku | PDIP (N) | 16 | 25 | TUBE | SN74LS670N |
| SN74LS670NE4 | ACTIVE | 0 to 70 | 2.45 | 1ku | PDIP (N) | 16 | 25 | TUBE | SN74LS670N |
SN74LS670 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LS670D | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS670D | SN74LS670D |
| SN74LS670DE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS670DE4 | SN74LS670DE4 |
| SN74LS670DG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS670DG4 | SN74LS670DG4 |
| SN74LS670DR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS670DR | SN74LS670DR |
| SN74LS670DRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS670DRE4 | SN74LS670DRE4 |
| SN74LS670DRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS670DRG4 | SN74LS670DRG4 |
| SN74LS670N | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LS670N | SN74LS670N |
| SN74LS670NE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LS670NE4 | SN74LS670NE4 |
SN74LS670 应用技术支持与电子电路设计开发资源下载
- SN74LS670 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)