SN74ABT833 描述The 'ABT833 8-bit to 9-bit parity transceivers are designed for communication   between data buses. When data is transmitted from the A bus to the B bus, a   parity bit is generated. When data is transmitted from the B bus to the A bus   with its corresponding parity bit, the open-collector parity-error (
) output   indicates whether or not an error in the B data has occurred. The output-enable   (
 and 
) inputs can be   used to disable the device so that the buses are effectively isolated. The   'ABT833 provide true data at their outputs.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and   monitors the parity of the I/O ports with the 
 flag. 
 is clocked into   the register on the rising edge of the clock (CLK) input.![]()
| SN74ABT833 | |
| Voltage Nodes(V) | 5 | 
| Vcc range(V) | 4.5 to 5.5 | 
| Input Level | TTL | 
| Output Level | TTL | 
| Output Drive(mA) | -32/64 | 
| No. of Outputs | 8 | 
| Logic | True | 
| Static Current | 19.12 | 
| tpd max(ns) | 5.3 | 
| Rating | Catalog | 
| Technology Family | ABT | 
| 器件 | 状态 | 温度 | 价格(美元) | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 | 
| SN74ABT833DW | ACTIVE | -40 to 85 | 1.80 | 1ku | SOIC (DW) | 24 | 25 | TUBE | ABT657A | 
| SN74ABT833DWE4 | ACTIVE | -40 to 85 | 1.80 | 1ku | SOIC (DW) | 24 | 25 | TUBE | ABT657A | 
| SN74ABT833DWG4 | ACTIVE | -40 to 85 | 1.80 | 1ku | SOIC (DW) | 24 | 25 | TUBE | ABT657A | 
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 | 
| SN74ABT833DW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ABT833DW | SN74ABT833DW | 
| SN74ABT833DWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ABT833DWE4 | SN74ABT833DWE4 | 
| SN74ABT833DWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ABT833DWG4 | SN74ABT833DWG4 |