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SN74ABT16841 具有三态输出的 20 位总线接口 D 类锁存器

These 20-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The 'ABT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 transparent D-type latches provide true data at the outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (1OE\ or 2OE\) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state

SN74ABT16841
Voltage Nodes(V) 5
Technology Family ABT
Rating Catalog
SN74ABT16841 特性
SN74ABT16841 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74ABT16841DGGR ACTIVE -40 to 85 2.64 | 1ku TSSOP (DGG) | 56 2000 | LARGE T&R  
SN74ABT16841DL ACTIVE -40 to 85 2.64 | 1ku SSOP (DL) | 56 20 | TUBE  
SN74ABT16841DLG4 ACTIVE -40 to 85 2.64 | 1ku SSOP (DL) | 56 20 | TUBE  
SN74ABT16841DLR ACTIVE -40 to 85 2.64 | 1ku SSOP (DL) | 56 1000 | LARGE T&R  
SN74ABT16841 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74ABT16841DGGR Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT16841DGGR SN74ABT16841DGGR
SN74ABT16841DL Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT16841DL SN74ABT16841DL
SN74ABT16841DLG4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT16841DLG4 SN74ABT16841DLG4
SN74ABT16841DLR Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT16841DLR SN74ABT16841DLR
SN74ABT16841 应用技术支持与电子电路设计开发资源下载
  1. SN74ABT16841 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
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  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
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  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)