SN54S175 具有清零功能的六路 D 类触发器
              These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to   implement D-type flip-flop logic. All have a direct clear input, and the '175,   'LS175, and 'S175 feature complementary outputs from each flip-flop. 
              Information at the D inputs meeting the setup time requirements is   transferred to the Q outputs on the positive-going edge of the clock pulse.   Clock triggering occurs at a particular voltage level and is not directly   related to the transition time of the positive-going pulse. When the clock input   is at either the high or low level, the D input signal has no effect at the   output.   
              
These circuits are fully compatible for use with most TTL circuits
              
                
                   | 
                  SN54S175 | 
                
                
                  | Voltage Nodes(V) | 
                  5   | 
                
                
                  | Rating | 
                  Military | 
                
              
              SN54S175 特性
              
              
                - '174, 'LS174, 'S174 Contain Six Flip-Flops with Single-Rail Outputs   
                
 - '175, 'LS175, 'S175 Contain Four Flip-Flops with Double-Rail Outputs   
                
 - Three Performance Ranges Offered: See Table Lower Right   
                
 - Buffered Clock and Direct Clear Inputs   
                
 - Individual Data Input to Each Flip-Flop   
                
 - Applications include:
                  
                      - Buffer/Storage Registers   
                      
 - Shift Registers   
                      
 - Pattern Generators
 
                  
                 
              
              SN54S175 芯片订购指南
              
                
                  | 器件 | 
                  状态 | 
                  温度 | 
                  价格(美元) | 
                  封装 | 引脚 | 
                  封装数量 | 封装载体 | 
                  丝印标记 | 
                
                
                  | SN54S175J | 
                  ACTIVE | 
                  -55 to 125 | 
                  4.24 | 1ku | 
                  CDIP (J) | 16 | 
                  1 | TUBE | 
                    | 
                
              
              SN54S175 质量与无铅数据
              
                
                  | 器件 | 
                  环保计划* | 
                  铅/焊球涂层 | 
                  MSL 等级/回流焊峰 | 
                  环保信息与无铅 (Pb-free) | 
                  DPPM / MTBF / FIT 率 | 
                
                
                  | SN54S175J | 
                  TBD | 
                  A42   | 
                  N/A for Pkg Type | 
                  SN54S175J | 
                  SN54S175J | 
                
              
              SN54S175 应用技术支持与电子电路设计开发资源下载
              
                - SN54S175 数据资料   dataSheet 下载.PDF 
 
                - TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls 
 
                - Shelf-Life Evaluation of Lead-Free Component Finishes  (PDF  1305 KB)
 
                - Understanding and Interpreting Standard-Logic Data Sheets  (PDF  857 KB)
 
                - TI IBIS File Creation, Validation, and Distribution Processes  (PDF  380 KB)
 
                - Implications of Slow or Floating CMOS Inputs  (PDF  101 KB)
 
                - CMOS Power Consumption and CPD Calculation  (PDF  89 KB)
 
                - Designing With Logic  (PDF  186 KB)
 
                - Live Insertion  (PDF  150 KB)
 
                - Input and Output Characteristics of Digital Integrated Circuits  (PDF  1708 KB)
 
                - Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc  (PDF  43 KB) 
 
                - HiRel Unitrode Power Management Brochure  (PDF  206 KB)
 
                - LOGIC Pocket Data Book  (PDF  6001 KB)
 
                - HiRel Unitrode Power Management Brochure  (PDF  206 KB)
 
                - Logic Cross-Reference (PDF  2938 KB)