These devices contain two independent J-K\ positive-edge-triggered   flip-flops. A low level at the preset or clear inputs sets or resets the outputs   regardless of the levels of the other inputs. When preset and clear are inactive   (high), data at the J and K\ inputs meeting the setup time requirements are   transferred to the outputs on the positive-going edge of the clock pulse. Clock   triggering occurs at a voltage level and is not directly related to the rise   time of the clock pulse. Following the hold time interval, data at the J and K\   inputs may be changed without affecting the levels at the outputs. These   versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying   J high. They also can perform as D-type flip-flops if J and K\ are tied   together.
| SN54LS109A | |
| Voltage Nodes(V) | 5 | 
| Rating | Military | 
| 器件 | 状态 | 温度 | 价格(美元) | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 | 
| SN54LS109AJ | ACTIVE | -55 to 125 | 4.24 | 1ku | CDIP (J) | 16 | 1 | TUBE | 
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 | 
| SN54LS109AJ | TBD | A42 | N/A for Pkg Type | SN54LS109AJ | SN54LS109AJ |