SN54HC74 具有清零和预设功能的双路 D 类上升沿触发器

The ’HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

	SN54HC74
Voltage Nodes(V)	6, 5, 2
Rating	Military

SN54HC74 特性

Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 40-uA Max ICC
Typical tpd = 15 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 uA Max

SN54HC74 芯片订购指南

器件	状态	温度	价格（美元）	封装 \| 引脚	封装数量 \| 封装载体	丝印标记
SN54HC74J	ACTIVE	-55 to 125	4.24 \| 1ku	CDIP (J) \| 14	1 \| TUBE

SN54HC74 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN54HC74J	TBD	A42	N/A for Pkg Type	SN54HC74J	SN54HC74J

SN54HC74 应用技术支持与电子电路设计开发资源下载

SN54HC74 数据资料 dataSheet 下载.PDF
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