SN54ALS996 8 位 D 类边沿触发读回锁存器

These 8-bit latches are designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. The Q outputs are designed with bus-driving capability.

The edge-triggered flip-flops enter the data on the low-to-high transition of the clock (CLK) input when the enable () input is low. Data can be read back onto the data inputs by taking the read () input low, in addition to having low. When EN\ is high, both the read-back and write modes are disabled. Transitions on should only be made with CLK high to prevent false clocking.

The polarity of the Q outputs can be controlled by the polarity (T/C\) input. When T/C\ is high, Q is the same as is stored in the flip-flops

	SN54ALS996
Voltage Nodes(V)	5
Vcc range(V)	4.5 to 5.5
Input Level	TTL
Output Level	TTL
Output Drive(mA)
Output	3S
No. of Bits	8
th(ns)
tpd max(ns)
tsu(ns)
Rating	Military
Technology Family	ALS

SN54ALS996 特性

• 3-State I/O-Type Read-Back Inputs
• Bus-Structured Pinout
• T/C\ Determines True or Complementary Data at Q Outputs
• Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

SN54ALS996 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN54ALS996J	ACTIVE	-55 to 125	6.67 | 1ku	CDIP (J) | 14	1 | TUBE
SNJ54ALS996FK	OBSOLETE	-55 to 125		LCCC (FK) | 24
SNJ54ALS996J	ACTIVE	-55 to 125	7.88 | 1ku	CDIP (J) | 14	1 | TUBE

SN54ALS996 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN54ALS996J	TBD	A42	N/A for Pkg Type	SN54ALS996J	SN54ALS996J
SNJ54ALS259J	TBD	A42	N/A for Pkg Type	SNJ54ALS259J	SNJ54ALS259J

SN54ALS996 应用技术支持与电子电路设计开发资源下载

1. SN54ALS996 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)