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SN54ALS175 具有清零功能的四路 D 类触发器

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits

SN54ALS175
Voltage Nodes(V) 5
Rating Military
SN54ALS175 特性
SN54ALS175 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN54ALS175J ACTIVE -55 to 125 4.24 | 1ku CDIP (J) | 16 1 | TUBE  
SN54ALS175 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN54ALS175J TBD A42 N/A for Pkg Type SN54ALS175J SN54ALS175J
SN54ALS175 应用技术支持与电子电路设计开发资源下载
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