SN54ABT843 具有三态输出的 9 位总线接口 D 类锁存器
The 'ABT843 9-bit latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The nine transparent D-type latches provide true data at the outputs.
A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly
SN54ABT843 特性
- State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
- High-Drive Outputs (-32-mA IOH, 64-mA IOL)
- Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs
SN54ABT843 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SNJ54ABT841FK |
ACTIVE |
-55 to 125 |
17.69 | 1ku |
LCCC (FK) | 28 |
1 | TUBE |
|
| SNJ54ABT841JT |
ACTIVE |
-55 to 125 |
16.69 | 1ku |
CDIP (JT) | 24 |
1 | TUBE |
|
| SNJ54ABT841W |
ACTIVE |
-55 to 125 |
15.36 | 1ku |
CFP (W) | 24 |
1 | TUBE |
|
SN54ABT843 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SNJ54ABT841FK |
TBD |
POST-PLATE |
N/A for Pkg Type |
SNJ54ABT841FK |
SNJ54ABT841FK |
| SNJ54ABT841JT |
TBD |
A42 |
N/A for Pkg Type |
SNJ54ABT841JT |
SNJ54ABT841JT |
| SNJ54ABT841W |
TBD |
Call TI |
N/A for Pkg Type |
SNJ54ABT841W |
SNJ54ABT841W |
SN54ABT843 应用技术支持与电子电路设计开发资源下载
- SN54ABT843 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)