CY54FCT373AT 具有三态输出的八路透明 D 类锁存器

The \x92FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down

	CY54FCT373AT
Technology Family	FCT
Rating	Military

CY54FCT373AT 特性

• Function and Pinout Compatible With FCT and F Logic
• Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
• Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
• Ioff Supports Partial-Power-Down Mode Operation
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)
• Matched Rise and Fall Times
• Fully Compatible With TTL Input and Output Logic Levels
• 3-State Outputs
• CY54FCT373T
  • 32-mA Output Sink Current
  • 12-mA Output Source Current
• CY74FCT373T
  • 64-mA Output Sink Current
  • 32-mA Output Source Current

CY54FCT373AT 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
CY54FCT373ATDMB	ACTIVE	-55 to 125	6.08 | 1ku	CDIP (J) | 20	1 | TUBE

CY54FCT373AT 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
CY54FCT373ATDMB	TBD	A42	N/A for Pkg Type	CY54FCT373ATDMB	CY54FCT373ATDMB

CY54FCT373AT 应用技术支持与电子电路设计开发资源下载

1. CY54FCT373AT 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)