CD54AC299 具有常见的并行 I/O 引脚和异步复位的 8 输入通用移位/存储寄存器
The RCA CD54/74AC299 and CD54/74AC323 and the CD54/74ACT299 and CD54/74ACT323 are 3-state, 8-input universal shift/storage registers with common parallel I/O pins. These devices use the RCA ADVANCED CMOS technology. These registers have four synchronous-operating modes controlled by the two select inputs as shown in the Mode Select (S0, S1) table. The Mode Select, the Serial Data (DSO, DS7), and the Parallel Data (I/O0 - I/O7) respond only to the LOW-TO-HIGH transition of the clock (CP) pulse. S0, S1 and Data inputs must be present one setup time prior to the positive transition of the clock.
With the CD54/74AC/ACT 299, the Master Reset (MR\) is an asynchronous active-LOW input. When MR\ is LOW, the register is cleared regardless of the status of all other inputs
|
CD54AC299 |
| Voltage Nodes(V) |
5, 3.3 |
| Technology Family |
AC |
| Rating |
Military |
CD54AC299 特性
- Buffered Inputs
- Typical propagation delay:
6 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF
- Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
- SCR-Latchup-resistant CMOS process and circuit design
- Speed of bipolar FAST*/AS/S with significantly reduced power consumption
- Balanced propagation delays
- AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
- ±24-mA output drive current
-Fanout to 15 FAST* ICs
-Drives 50-ohm transmission lines
- Characterized for operation from –40° to 85°C
CD54AC299 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD54AC299F |
ACTIVE |
-55 to 125 |
5.09 | 1ku |
CDIP (JT) | 20 |
1 | TUBE |
|
| CD54AC299F3A |
ACTIVE |
-55 to 125 |
5.91 | 1ku |
CDIP (JT) | 20 |
1 | TUBE |
|
CD54AC299 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD54AC299F |
TBD |
A42 |
N/A for Pkg Type |
CD54AC299F |
CD54AC299F |
| CD54AC299F3A |
TBD |
A42 |
N/A for Pkg Type |
CD54AC299F3A |
CD54AC299F3A |
CD54AC299 应用技术支持与电子电路设计开发资源下载
- CD54AC299 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)