CD4027B-MIL CMOS 双路 J-K 主/从触发器
CD4027B is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master-slave flip-flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input signals. Buffered Q and Q\ signals are provided as outputs. This input-ouput arrangement provides for compatible operation with the RCA-CD4013B dual D-type flip-flop.
The CD4027B is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input
|
CD4027B-MIL |
| Voltage Nodes(V) |
5, 10, 15 |
| Technology Family |
CD4000 |
| Rating |
Military |
CD4027B-MIL 特性
- Set-Reset capability
- Static flip-flop operation — retains state indefinitely with clock level either "high" or "low"
- Medium speed operation — 16 MHz (typ.) clock toggle rate at 10 V
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Registers, counters, control circuits
CD4027B-MIL 芯片订购指南
| 器件 |
状态 |
温度 |
|
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD4027BF |
ACTIVE |
-55 to 125 |
4.15 | 1ku |
CDIP (J) | 16 |
1 | TUBE |
|
| CD4027BF3A |
ACTIVE |
-55 to 125 |
4.93 | 1ku |
CDIP (J) | 16 |
1 | TUBE |
|
| JM38510/05152BEA |
ACTIVE |
-55 to 125 |
20.82 | 1ku |
CDIP (J) | 16 |
1 | TUBE |
|
CD4027B-MIL 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD4027BF |
TBD |
A42 |
N/A for Pkg Type |
CD4027BF |
CD4027BF |
| CD4027BF3A |
TBD |
A42 |
N/A for Pkg Type |
CD4027BF3A |
CD4027BF3A |
| JM38510/05152BEA |
TBD |
A42 |
N/A for Pkg Type |
JM38510/05152BEA |
JM38510/05152BEA |
CD4027B-MIL 应用技术支持与电子电路设计开发资源下载
- CD4027B-MIL 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)