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ADS6242 具有串行 LVDS 输出的双路 14 位 65MSPS ADC

ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design.


ADS6222 ADS6223 ADS6224 ADS6225 ADS6242 ADS6243 ADS6244 ADS6245
Resolution(Bits) 12 12 12 12 14 14 14 14
Sample Rate (max) 65MSPS 80MSPS 105MSPS 125MSPS 65MSPS 80MSPS 105MSPS 125MSPS
Architecture Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline
Power Consumption(Typ)(mW) 630 760 900 1000 630 760 900 1000
SINAD(dB) 71 70.9 70 70 73.7 73.5 72 72.3
SNR(dB) 71.2 71.1 70.6 70.3 74 73.8 73 73.2
SFDR(dB) 88 87 81 83 88 87.5 81 83
DNL(Max)(+/-LSB) 4 1.8 2 2 4 2 2.5 2.5
INL(Max)(+/-LSB) 1 2 2.5 2.5 5 4.5 5 5
No Missing Codes(Bits) 12 12 12 12 14 14 14 14
ENOB(Bits) 11.5 11.5 11.4 11.4 12 11.9 11.7 11.7
No. of Supplies 2 2 2 2 2 2 2 2
Analog Voltage AV/DD(Min)(V) 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0
Analog Voltage AV/DD(Max)(V) 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
Logic Voltage DV/DD(Min)(V) 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0
Logic Voltage DV/DD(Max)(V) 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
Input Configuration Range 2V (p-p) 2V (p-p) 2V (p-p) 2V (p-p) 2V (p-p) 2V (p-p) 2V (p-p) 2V (p-p)
Reference Mode Int and Ext Int and Ext Int and Ext Int and Ext Int and Ext Int and Ext Int and Ext Int and Ext
Rating Catalog Catalog Catalog Catalog Catalog Catalog Catalog Catalog
Pin/Package 48VQFN 48VQFN 48VQFN 48VQFN 48VQFN 48VQFN 48VQFN 48VQFN
# Input Channels 2 2 2 2 2 2 2 2
Operating Temp Range(Celsius) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85
ADS6242 特性
ADS6242 芯片订购指南
器件 状态 温度 (oC) 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
ADS6242IRGZ25 PREVIEW -40 to 85 VQFN (RGZ) | 48 25 | SMALL T&R AZ6242
ADS6242IRGZR ACTIVE -40 to 85 43.75 | 100u VQFN (RGZ) | 48 3000 | LARGE T&R AZ6242
ADS6242IRGZRG4 ACTIVE -40 to 85 43.75 | 100u VQFN (RGZ) | 48 3000 | LARGE T&R AZ6242
ADS6242IRGZT ACTIVE -40 to 85 45.00 | 100u VQFN (RGZ) | 48 250 | SMALL T&R AZ6242
ADS6242IRGZTG4 ACTIVE -40 to 85 45.00 | 100u VQFN (RGZ) | 48 250 | SMALL T&R AZ6242
ADS6242 工具与软件
名称 型号 公司 工具/软件类型
ADS6242 评估模块 ADS6242EVM Texas Instruments 开发电路板/EVM
ADC 谐波计算器 ADC-HARMONIC-CALC Texas Instruments 计算实用程序
用于模数转换器的抗混淆计算工具 ANTIALIASINGCALC Texas Instruments 计算实用程序
运算放大器至 ADC 电路拓扑计算器 ADC-INPUT-CALC Texas Instruments 计算实用程序
ADS6242 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
ADS6242IRGZ25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6242IRGZ25 ADS6242IRGZ25
ADS6242IRGZR Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6242IRGZR ADS6242IRGZR
ADS6242IRGZRG4 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6242IRGZRG4 ADS6242IRGZRG4
ADS6242IRGZT Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6242IRGZT ADS6242IRGZT
ADS6242IRGZTG4 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6242IRGZTG4 ADS6242IRGZTG4
ADS6242 应用技术支持与电子电路设计开发资源下载
  1. ADS6242 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器仪ADC 模数转换器产品选型与价格 . xls
  3. 模数规格和性能特性术语表 (Rev. A) (PDF 1993 KB)
  4. 所选封装材料的热学和电学性质 (PDF 645 KB)
  5. 高速数据转换 (PDF 1967 KB)
  6. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  7. A Spreadsheet for Calculating the Frequency Response of the ADS1250-54 (PDF 461 KB)
  8. A Spreadsheet for Calculating the Frequency Response of the ADS1250-54
  9. Understanding the ADS1251, ADS1253, and ADS1254 Input Circuitry (PDF 39 KB)
  10. Analog-to-Digital Converter Grounding Practices Affect System Performance (PDF 56 KB)
  11. Principles of Data Acquisition and Conversion (PDF 50 KB)
  12. Interleaving Analog-to-Digital Converters (PDF 64 KB)
  13. What Designers Should Know About Data Converter Drift (PDF 95 KB)
  14. Giving Delta-Sigma Converters a Gain Boost with a Front End Analog Gain Stage (PDF 70 KB)
  15. Programming Tricks for Higher Conversion Speeds Utilizing Delta Sigma Converters (PDF 105 KB)