The STR910F devices employ an ARM966E-STM core that brings substantial benefits compared to ARM7TDMI cores. The ARM966E-STM CPU core accesses its instruction and data memories using two separate internal busses, enabling simultaneous access of both code and data. Each of these memories is attached to the core through a highly optimized Tightly-Coupled Memory (TCM) interface for rapid access. The STR910F exploits this architecture by placing a high-speed burst Flash memory on the Instruction TCM, and a zero-latency SRAM on the Data TCM. The result is 96 MIPS peak code execution at 96 MHz (the highest peak performance for general-purpose Flash ARM-based MCUs), and extremely efficient data movement between the CPU core and SRAM. In contrast, the ARM7TDMI CPU core shares a single bus for access to its instruction and data memories, making simultaneous access impossible. Additionally, the ARM966E-STM core supports single-cycle Digital Signal Processing (DSP) instructions, enabling the STR910F to satisfy both control and signal-processing requirements, giving clear advantages over traditional solutions based on separate DSP and control processors. All of these benefits of the ARM966E-STM core position the STR910F family at the top end of the embedded-Flash 32-bit microcontroller market.

Traditionally, ARM9E cores are used to build ROMless microprocessors that have a complex Memory Management Unit (MMU) operating with internal cache and external synchronous RAM, all loaded at boot-up from an external Flash memory. However, the STR910F was designed to bring many benefits of the ARM9E core without the expense of traditional cache and external memories, realizing a compact, single-device Flash MCU. Instead of an MMU with cache, the STR910F supports a simple memory model well suited for compact Real-Time Operating Systems (RTOS). It also uses an innovative memory accelerator with a pre-fetch queue and branch-cache system to boost performance during non-sequential code execution from burst Flash memory, with better real-time control behavior than that of a traditional cache memory.

The STR910F was given large memories to support the use of RTOS and TCP/IP stacks, in addition to complex control applications. SRAM sizes range up to 96 Kbytes, the largest SRAM of all general-purpose ARM-based Flash MCUs in the market today, ideal for larger packet buffers enabling faster serial communications. Uniquely, this SRAM can be protected by a battery or super-capacitor connected to the battery input pin, and optionally the SRAM contents can be automatically destroyed for secure applications in response to a signal on the STR910F’s tamper-detection input pin. Flash memory sizes range up to 544 Kbytes, and is configured into dual banks of read-while-write memory to support robust In-Application Programming for remote firmware updates, and also for EEPROM emulation. Each of the SRAM and Flash memories may be used for either instructions or data.

There are many high-speed communication channels on the STR910F, and up to nine full-featured Direct Memory Access (DMA) channels to support them, making data movement between peripherals and memory almost transparent to the CPU, freeing the CPU to perform comprehensive real-time control tasks. These DMA controllers effectively allow peripherals on the Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB) to act as a master to the SRAM, sharing SRAM access with the CPU through a specially designed arbitrator for extremely streamlined data flow. For example, the Ethernet DMA controller can support the movement of 91 Mbps of raw Ethernet frames between the MAC (Media Access Controller) and the SRAM, with only 10% CPU loading.

STR910F MCU series support a full set of peripherals in addition to the Ethernet MAC. They include USB Full Speed, CAN, three UART/IrDA, two SPI, two I2C, eight channel 10-bit ADC, four 16-bit timers, a 3-phase AC motor control unit, complete supervisor functions with Low Voltage Reset and Brown-out Detect, a full-featured real-time clock, an external memory interface, an ETM9 debug and trace interface, and up to 80 5V tolerant I/O.

“The STR910F combines a number of ST’s particular strengths, including our long experience in incorporating ARM cores into both general-purpose and application-specific microcontrollers,” said Mark Rootz, Marketing Manager for ARM9-based products at ST’s Microcontroller Division. “The combination of the ARM966E-S core and the industry’s largest embedded memories, coupled with the built-in Ethernet, USB, and CAN connectivity, makes this series ideal for applications across the whole spectrum of embedded control.”

Leveraging the Company’s strengths in power management, the STR910F family also exhibits impressive power conservation and supervisor features. Power consumption can be dynamically adjusted, giving the CPU the ability to gate and scale the system and peripheral clocks at any time to balance performance demand and power consumption, including a Sleep mode drawing only 55μA, typical. When main power to the device is shut off or is absent because of a fault, the STR910F will automatically switch to the battery supply pin to keep the real-time clock active. The embedded real-time clock has features typically found only on external RTC devices. It has full calendar and alarm functions, it will time-stamp an event on the Tamper input pin, and it draws less than 1μA on the battery supply pin across the entire -40oC to +85oC temperature range. These features make the STR910F ideal for portable, battery-powered, secure applications.

Starting mid-May 2006, STR910F users will enjoy comprehensive support from ST and third parties, with starter kits from US$199 from Hitex, IAR, Keil, and Raisonance. Kits include compiler and debugger (limited code size), a JTAG debugging and programming cable, code examples, and all necessary hardware to begin a design. ST provides an evaluation board, the STR910-EVAL, at US$249, for extensive exercising and hardware evaluation of all interfaces and I/O of the STR910F. Demonstration code for Ethernet, USB, CAN, and all other major chip functions based on a common Hardware Abstraction Layer (HAL) library is available free of charge from ST. To assist with configuring the STR910F’s flexible I/O matrix and clock functions, ST offers CAPS (Configuration and Programming Software), a free software tool used to graphically choose pin functions and clock distribution. CAPS automatically generates a C header file that reflects all of the pin and clock choices, saving time and preventing error. RTOS and TCP/IP support will be available mid-May from CMX, Micrium, Segger, Keil, and NexGen Software with many more to be added in 2006.

Six part numbers are offered, all in lead-free packages. Devices are packaged as LQFP80 and LQFP128, with the LQFP128 packages offering the Ethernet Media Independent Interface (MII) and the external memory bus interface. SRAM ranges from 64K to 96Kbytes and Flash memory ranges from 288K to 544Kbytes. The core operates at 1.8V +/- 10%, and the I/O ring at 2.7V to 3.6V, over a temperature range of -40oC to +85oC.

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