TSB43AB21A 集成 1394a、400Mbps、1 端口物理层 (PHY) 的 OHCI 1.1、1394a 链路层控制器

The Texas Instruments TSB43AB21A device is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification (Revision 1.1), IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification (Release 1.1). It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB21A device provides one 1394 port. The TSB43AB21A device also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements.

As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable

	TSB43AB21A
Speed(Max)(Mbps)	400
FIFO(kb)	9
Pin/Package	128TQFP
Operating Temperature Range(°C)	0 to 70
Rating	Catalog

TSB43AB21A 特性

• Fully compliant with 1394 Open Host Controller Interface Specification (Release 1.1)
• Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std 1394a-2000
• Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394
• Compliant with Intel Mobile Power Guideline 2000
• Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume
• Power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, PCI power management for link-layer, and inactive ports powered down
• Ultralow-power sleep mode
• One IEEE Std 1394a-2000 fully compliant cable port at 100M bits/s, 200M bits/s, or 400M bits/s
• Cable port monitors line conditions for active connection to remote node
• Cable power presence monitoring
• 1.8-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Physical write posting of up to three outstanding transactions
• PCI burst transfers and deep FIFOs to tolerate large host latency
• PCI_CLKRUN\ protocol
• External cycle timer control for customized synchronization
• Extended resume signaling for compatibility with legacy DV components
• PHY-link logic performs system initialization and arbitration functions
• PHY-link encode and decode functions included for data-strobe bit level encoding
• PHY-link incoming data resynchronized to local clock
• Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, or 400M bits/s

TSB43AB21A 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
TSB43AB21AIPDT	NRND	-40 to 85	4.90 | 1ku	TQFP (PDT) | 128	90 | SMALL T&R
TSB43AB21APDT	ACTIVE	0 to 70	4.45 | 1ku	TQFP (PDT) | 128	90 | JEDEC TRAY (5+1)
TSB43AB21APDTG4	ACTIVE	0 to 70	4.45 | 1ku	TQFP (PDT) | 128	90 | JEDEC TRAY (10+1)

TSB43AB21A 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
TSB43AB21AIPDT	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-3-260C-168 HR	TSB43AB21AIPDT	TSB43AB21AIPDT
TSB43AB21APDT	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-3-260C-168 HR	TSB43AB21APDT	TSB43AB21APDT
TSB43AB21APDTG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-3-260C-168 HR	TSB43AB21APDTG4	TSB43AB21APDTG4

TSB43AB21A 应用技术支持与电子电路设计开发资源下载

1. TSB43AB21A 数据资料 dataSheet 下载.PDF
2. TI 德州仪器1394 集成器件产品选型与价格 . xls
3. Analog Signal Chain Guide (8.62 MB)
4. Industrial Interface IC Solutions (101 KB)