TS5N412 4 位 2 选 1 FET 多路复用器/多路解复用器高带宽总线开关
The TS5N412 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the TS5N412 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.
The TS5N412 is a 4-bit 1-of-2 multiplexer/demultiplexer with a single output-enable (OE) input. The select (S) inputs control the data path of the multiplexer/demultiplexer. When OE is low, the multiplexer/demultiplexer is enabled and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the multiplexer/demultiplexer is disabled and a high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
| TS5N412 | |
| Vcc min(V) | 4.75 |
| Vcc max(V) | 5.25 |
| ron(max)(ohms) | 7.5,12.5 |
| ICC(uA) | 10000 |
| tpd max(ns) | 3 |
TS5N412 特性
- Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 3
Typ)
- 0- to 10-V Switching on Data I/O Ports
- Bidirectional Data Flow With Near-Zero Propagation Delay
- Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 20 pF Max, B Port)
- VCC Operating Range From 4.75 V to 5.25 V
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
- Supports Both Digital and Analog Applications
- APPLICATIONS
- PCI Interface
- Differential Signal Interface
- Memory Interleaving
- Bus Isolation
- Low-Distortion Signal Gating
TS5N412 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| TS5N412DBQR | ACTIVE | 0 to 70 | 1.55 | 1ku | SSOP/QSOP (DBQ) | 16 | 2500 | LARGE T&R | |
| TS5N412DBQRE4 | ACTIVE | 0 to 70 | 1.55 | 1ku | SSOP/QSOP (DBQ) | 16 | 2500 | LARGE T&R | |
| TS5N412DBQRG4 | ACTIVE | 0 to 70 | 1.55 | 1ku | SSOP/QSOP (DBQ) | 16 | 2500 | LARGE T&R | |
| TS5N412PW | ACTIVE | 0 to 70 | 1.85 | 1ku | TSSOP (PW) | 20 | 70 | TUBE | |
| TS5N412PWE4 | ACTIVE | 0 to 70 | 1.85 | 1ku | TSSOP (PW) | 20 | 70 | TUBE | |
| TS5N412PWG4 | ACTIVE | 0 to 70 | 1.85 | 1ku | TSSOP (PW) | 20 | 70 | TUBE | |
| TS5N412PWR | ACTIVE | 0 to 70 | 1.55 | 1ku | TSSOP (PW) | 20 | 2000 | LARGE T&R | |
| TS5N412PWRE4 | ACTIVE | 0 to 70 | 1.55 | 1ku | TSSOP (PW) | 20 | 2000 | LARGE T&R | |
| TS5N412PWRG4 | ACTIVE | 0 to 70 | 1.55 | 1ku | TSSOP (PW) | 20 | 2000 | LARGE T&R |
TS5N412 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| TS5N412DBQR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-2-260C-1 YEAR | TS5N412DBQR | TS5N412DBQR |
| TS5N412DBQRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-2-260C-1 YEAR | TS5N412DBQRE4 | TS5N412DBQRE4 |
| TS5N412DBQRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-2-260C-1 YEAR | TS5N412DBQRG4 | TS5N412DBQRG4 |
| TS5N412PW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | TS5N412PW | TS5N412PW |
| TS5N412PWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | TS5N412PWE4 | TS5N412PWE4 |
| TS5N412PWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | TS5N412PWG4 | TS5N412PWG4 |
| TS5N412PWR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | TS5N412PWR | TS5N412PWR |
| TS5N412PWRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | TS5N412PWRE4 | TS5N412PWRE4 |
| TS5N412PWRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | TS5N412PWRG4 | TS5N412PWRG4 |
TS5N412 应用技术支持与电子电路设计开发资源下载
- TS5N412 数据资料 dataSheet 下载.PDF
- TI 德州仪器信号开关产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- 防止模拟开关的额外功耗 (PDF 392 KB) (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)