TLK6002 2 通道 0.47Gbps 至 6.25Gbps 多速率收发器
The TLK6002 is a member of a portfolio of multi-gigabit transceivers, intended for use in ultra-high-speed bi-directional point-to-point data transmission systems. It is specifically intended for base station RRH (Remote Radio Head) application, but may also be used in other high speed applications. The TLK6002 supports a serial interface speed of 0.470 Gbps to 6.25 Gbps. Rate support includes all the CPRI and OBSAI rates (0.6144/0.768/1.2288/1.536/2.4576/3.072/4.9152/6.144 Gbps) using a single fixed reference clock frequency (either 122.88 MHz or 153.6 MHz).
TLK6002 20-bit parallel interface operates in 1.5V or 1.8V HSTL single-ended format. The 20-bit interface allows low speed signals on the parallel side and therefore enabling the use of low cost FPGA in the system design
|
TLK6002 |
Gbps per Serial Channel(Min) |
0.47 |
Gbps per Serial Channel(Max) |
6.250 |
Power Consumption(Nom)(mW) |
1970 |
Number of Serial Channels |
2 |
Parallel Bus Width |
up to 20 |
Parallel I/F |
HSTL |
Serial I/F |
CML,CPRI,OBSAI |
Operating Temperature Range(C) |
-40 to 85 |
Pin/Package |
324BGA |
Power Supply(V) |
1.0,1.5,1.8 |
Vid(Min)(Vp-p) |
0.25 |
Vid(Max)(Vp-p) |
2.0 |
Vod(Min)(Vp-p) |
1.0 |
Vod(Max)(Vp-p) |
2.0 |
TLK6002 特性
- Dual Channel 470Mbps to 6.25Gbps Continuous/Multi-Rate Transceiver
- Supports all CPRI and OBSAI Data Rates
- Integrated Latency Measurement Function, Accuracy of ±814 ps
- CPRI/OBSAI Automated Rate Sense (ARS) Function
- Supports SERDES Operation, 8B/10B Data Modes (20-bit and 16-bit + Controls)
- 20-bit HSTL Single-Ended Parallel Data Interface (Integrated Source and
End Termination)
- Shared or Independent Reference Clock per Channel
- Latency/Depth Configurable Transmit and Receive FIFOs.
- Loopback Capability (Serial and Parallel Side), OBSAI Compliant
- Supports Serial Retime Operation
- Supports PRBS (27–1), (223 – 1) and (231–1) and
CRPAT Long/Short Generation and Verification
- Dual Power Supply: 1.0V Core, and 1.5V/1.8V I/O Nominal Supply
- Serial Side Three Tap Transmit De-emphasis and Receive Adaptive Equalization
to Allow Extended Backplane Reach
- Programmable Output Swing on Serial Output
- Minimum Receiver Differential Input Thresholds of 100mVdfpp
- Loss of Signal (LOS) detection (≤75 mVdfpp)
- Interface to Back Plane, Copper Cables, or Optical Modules
- Hot Plug Protection
- JTAG; IEEE 1149.1 /1149.6 Test Interface
- MDIO; IEEE 802.3 Clause-22 Support
TLK6002 芯片订购指南
器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
TLK6002ZEU |
ACTIVE |
-40 to 85 |
35.00 | 1ku |
BGA (ZEU) | 324 |
84 | JEDEC TRAY (10+1) |
|
TLK6002 质量与无铅数据
器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
TLK6002ZEU |
TBD |
SNPB |
Level-4-220C-72 HR |
TLK6002ZEU |
TLK6002ZEU |
TLK6002 应用技术支持与电子电路设计开发资源下载
- TLK6002 数据资料 dataSheet 下载.PDF
- TI 德州仪器串行器和解串器选型与价格 . xls
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
- 高性能SERDES及其在CPRI 接口的应用分析 (zhca076.HTM, 8 KB)
- 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
- 接口选择指南 (Rev. D) (PDF 2994 KB)
- Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
- Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
- Isolated RS-485 Reference Design (PDF 80 KB)
- 无铅组件涂层的保存期评估 (PDF 1305 KB)
- Analog Signal Chain Guide (8.62 MB)
- Industrial Interface IC Solutions (101 KB)
TLK6002 工具和软件