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SN74VMEH22501 具有三态输出的 8 位通用总线收发器和两个 1 位总线收发器

The SN74VMEH22501 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is designed for 3.3-V VCC operation with 5-V tolerant inputs. The UBTTM transceiver allows transparent, latched, and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards operating at LVTTL logic levels and VME64, VME64x, or VME320(1) backplane topologies.

High-speed backplane operation is a direct result of the improved OECTM circuitry and high drive that has been designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive loads and include pseudo-ETL input thresholds ( 1/2 VCC ± 50 mV) for increased noise immunity. These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5. With proper design of a 21-slot VME system, a designer can achieve 320-Mbyte transfer rates on linear backplanes and, possibly, 1-Gbyte transfer rates on the VME320 backplane.

All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs.

Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, output-enable (OE and OEBY) inputs should be tied to VCC through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this input

SN74VMEH22501
Voltage Nodes(V) 3.3
Rating Catalog
Technology Family VME
SN74VMEH22501 特性
SN74VMEH22501 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
74VMEH22501DGGRE4 ACTIVE 0 to 85 3.75 | 1ku TSSOP (DGG) | 48 2000 | LARGE T&R  
74VMEH22501DGGRG4 ACTIVE 0 to 85 3.75 | 1ku TSSOP (DGG) | 48 2000 | LARGE T&R  
74VMEH22501DGVRE4 ACTIVE 0 to 85 3.75 | 1ku TVSOP (DGV) | 48 2000 | LARGE T&R  
74VMEH22501DGVRG4 ACTIVE 0 to 85 3.75 | 1ku TVSOP (DGV) | 48 2000 | LARGE T&R  
SN74VMEH22501DGG PREVIEW 0 to 85 TSSOP (DGG) | 48 40 | TUBE  
SN74VMEH22501DGGR ACTIVE 0 to 85 3.75 | 1ku TSSOP (DGG) | 48 2000 | LARGE T&R  
SN74VMEH22501DGVR ACTIVE 0 to 85 3.75 | 1ku TVSOP (DGV) | 48 2000 | LARGE T&R  
SN74VMEH22501GQLR NRND 0 to 85 5.60 | 1ku BGA MICROSTAR JUNIOR (GQL) | 56 1000 | LARGE T&R  
SN74VMEH22501ZQLR ACTIVE -40 to 85 5.60 | 1ku BGA MICROSTAR JUNIOR (ZQL) | 56 1000 | LARGE T&R  
SN74VMEH22501 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
74VMEH22501DGGRE4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74VMEH22501DGGRE4 74VMEH22501DGGRE4
74VMEH22501DGGRG4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74VMEH22501DGGRG4 74VMEH22501DGGRG4
74VMEH22501DGVRE4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74VMEH22501DGVRE4 74VMEH22501DGVRE4
74VMEH22501DGVRG4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74VMEH22501DGVRG4 74VMEH22501DGVRG4
SN74VMEH22501DGG Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74VMEH22501DGG SN74VMEH22501DGG
SN74VMEH22501DGGR Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74VMEH22501DGGR SN74VMEH22501DGGR
SN74VMEH22501DGVR Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74VMEH22501DGVR SN74VMEH22501DGVR
SN74VMEH22501GQLR TBD SNPB Level-1-240C-UNLIM SN74VMEH22501GQLR SN74VMEH22501GQLR
SN74VMEH22501ZQLR Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74VMEH22501ZQLR SN74VMEH22501ZQLR
SN74VMEH22501 应用技术支持与电子电路设计开发资源下载
  1. SN74VMEH22501 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器通用总线功能产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)