SN74V3650 2048 x 36 同步 FIFO 存储器
The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits:
- Flexible ×36/×18/×9 bus matching on both read and write ports
- The period required by the retransmit operation is fixed and short.
- The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short.
- High-density offerings up to 1 Mbit
Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes
|
SN74V3640 |
SN74V3650 |
SN74V3660 |
SN74V3670 |
SN74V3680 |
SN74V3690 |
| Depth |
1024 |
2048 |
4096 |
8192 |
16384 |
32768 |
| Width |
36 |
36 |
36 |
36 |
36 |
36 |
| Fmax(MHz) |
166 |
166 |
166 |
166 |
166 |
166 |
| Sync/Async |
S |
S |
S |
S |
S |
S |
| Voltage Nodes(V) |
3.3 |
3.3 |
3.3 |
3.3 |
3.3 |
3.3 |
| Vcc range(V) |
3.15 to 3.45 |
3.15 to 3.45 |
3.15 to 3.45 |
3.15 to 3.45 |
3.15 to 3.45 |
3.15 to 3.45 |
| Flags Empty |
1 |
1 |
1 |
1 |
1 |
1 |
| Flags Full |
1 |
1 |
1 |
1 |
1 |
1 |
| Flags Half |
1 |
1 |
1 |
1 |
1 |
1 |
| Technology Family |
V |
V |
V |
V |
V |
V |
| Output Drive(mA) |
-2/8 |
-2/8 |
-2/8 |
-2/8 |
-2/8 |
-2/8 |
| Rating |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
SN74V3650 特性
- Choice of Memory Organizations
- SN74V3640 - 1024 × 36 Bit
- SN74V3650 - 2048 × 36 Bit
- SN74V3660 - 4096 × 36 Bit
- SN74V3670 - 8192 × 36 Bit
- SN74V3680 - 16384 × 36 Bit
- SN74V3690 - 32768 × 36 Bit
- 166-MHz Operation (6-ns Read/Write Cycle Time)
- User-Selectable Input and Output Port Bus Sizing
- ×36 in to ×36 out
- ×36 in to ×18 out
- ×36 in to ×9 out
- ×18 in to ×36 out
- ×9 in to ×36 out
- Big-Endian/Little-Endian User-Selectable Byte Representation
- 5-V-Tolerant Inputs
- Fixed, Low, First-Word Latency
- Zero-Latency Retransmit
- Master Reset Clears Entire FIFO
- Partial Reset Clears Data, but Retains Programmable Settings
SN74V3650 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN74V3650-6PEU |
ACTIVE |
0 to 70 |
14.36 | 1ku |
LQFP (PBK) | 128 |
72 | JEDEC TRAY (5+1) |
|
| SN74V3650-7PEU |
ACTIVE |
0 to 70 |
13.90 | 1ku |
LQFP (PBK) | 128 |
72 | JEDEC TRAY (5+1) |
|
SN74V3650 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN74V3650-6PEU |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-4-260C-72 HR |
SN74V3650-6PEU |
SN74V3650-6PEU |
| SN74V3650-7PEU |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-4-260C-72 HR |
SN74V3650-7PEU |
SN74V3650-7PEU |
SN74V3650 应用技术支持与电子电路设计开发资源下载
- SN74V3650 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)