SN74SSTVF16859 具有 SSTL_2 输入和输出的 13 位至 26 位寄存缓冲器

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads.

The SN74SSTVF16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level

	SN74SSTVF16859
Voltage Nodes(V)	2.5
Vcc range(V)	2.3 to 2.7
Input Level	SSTL_2
Output Level	SSTL_2
Logic	True
No. of Outputs	26
Output Drive(mA)	-16/16
Technology Family	SSTV
Rating	Catalog

SN74SSTVF16859 特性

• Member of the Texas Instruments WidebusTM Family
• Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700
• Operates at 2.5 V to 2.7 V for PC3200 (QFN Package)
• Pinout and Functionality Compatible With JEDEC Standard SSTV16859
• 600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV16859 in PC2700 DIMM Applications
• 1-to-2 Outputs to Support Stacked DDR DIMMs
• Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
• Outputs Meet SSTL_2 Class I Specifications
• Supports SSTL_2 Data Inputs
• Differential Clock (CLK and CLK\) Inputs
• Supports LVCMOS Switching Levels on the RESET\ Input
• RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
• Pinout Optimizes DIMM PCB Layout
• Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
• ESD Protection Exceeds JESD22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

SN74SSTVF16859 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
74SSTVF16859G4RG4	ACTIVE	0 to 70	2.75 | 1ku	VQFN (RGQ) | 56	2000 | LARGE T&R
SN74SSTVF16859G4R	ACTIVE	0 to 70	2.75 | 1ku	VQFN (RGQ) | 56	2000 | LARGE T&R
SN74SSTVF16859GR	ACTIVE	0 to 70	2.75 | 1ku	TSSOP (DGG) | 64	2000 | LARGE T&R
SN74SSTVF16859GRG4	ACTIVE	0 to 70	2.75 | 1ku	TSSOP (DGG) | 64	2000 | LARGE T&R
SN74SSTVF16859S8	ACTIVE	0 to 70	2.75 | 1ku	VQFN (RGQ) | 56	2000 | LARGE T&R
SN74SSTVF16859S8G3	ACTIVE	0 to 70	2.75 | 1ku	VQFN (RGQ) | 56	2000 | LARGE T&R
SN74SSTVF16859SR	ACTIVE	0 to 70	2.75 | 1ku	VQFN (RGQ) | 56	2000 | LARGE T&R
SN74SSTVF16859SRG3	ACTIVE	0 to 70		VQFN (RGQ) | 56

SN74SSTVF16859 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
74SSTVF16859G4RG4	Green (RoHS & no Sb/Br)	CU NIPDAUAG	Level-3-260C-168 HR	74SSTVF16859G4RG4	74SSTVF16859G4RG4
SN74SSTVF16859G4R	Green (RoHS & no Sb/Br)	CU NIPDAUAG	Level-3-260C-168 HR	SN74SSTVF16859G4R	SN74SSTVF16859G4R
SN74SSTVF16859GR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	SN74SSTVF16859GR	SN74SSTVF16859GR
SN74SSTVF16859GRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	SN74SSTVF16859GRG4	SN74SSTVF16859GRG4
SN74SSTVF16859S8	Green (RoHS & no Sb/Br)	CU SN	Level-3-260C-168 HR	SN74SSTVF16859S8	SN74SSTVF16859S8
SN74SSTVF16859S8G3	Green (RoHS & no Sb/Br)	CU SN	Level-3-260C-168 HR	SN74SSTVF16859S8G3	SN74SSTVF16859S8G3
SN74SSTVF16859SR	TBD	CU SNPB	Level-3-235C-168 HR	SN74SSTVF16859SR	SN74SSTVF16859SR

SN74SSTVF16859 应用技术支持与电子电路设计开发资源下载

1. SN74SSTVF16859 数据资料 dataSheet 下载.PDF
2. TI 德州仪器特殊逻辑产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)