SN74SSTU32864 具有 SSTL_18 输入和输出的 25 位可配置寄存缓冲器

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.

All inputs are SSTL_18, except the LVCMOS reset (RESET)\ and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.

The SN74SSTU32864 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high).

	SN74SSTU32864
Voltage Nodes(V)	1.8
Vcc range(V)	1.7 to 1.9
Input Level	SSTL_18
Output Level	SSTL_18
Logic	True
No. of Outputs	25
Output Drive(mA)	-8/8
Static Current	40 mA
tpd max(ns)	2.5
Technology Family	SSSTL
Rating	Catalog

SN74SSTU32864 特性

• Member of the Texas Instruments Widebus+TM Family
• Pinout Optimizes DDR-II DIMM PCB Layout
• Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer
• Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption
• Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
• Supports SSTL_18 Data Inputs
• Differential Clock (CLK and CLK\) Inputs
• Supports LVCMOS Switching Levels on the Control and RESET\ Inputs
• RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 5000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

SN74SSTU32864 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74SSTU32864GKER	ACTIVE	0 to 70	6.60 | 1ku	LFBGA (GKE) | 96	1000 | LARGE T&R
SN74SSTU32864ZKER	ACTIVE	0 to 70	6.60 | 1ku	LFBGA (ZKE) | 96	1000 | LARGE T&R

SN74SSTU32864 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74SSTU32864GKER	TBD	SNPB	Level-3-220C-168 HR	SN74SSTU32864GKER	SN74SSTU32864GKER
SN74SSTU32864ZKER	Green (RoHS & no Sb/Br)	SNAGCU	Level-3-260C-168 HR	SN74SSTU32864ZKER	SN74SSTU32864ZKER

SN74SSTU32864 应用技术支持与电子电路设计开发资源下载

1. SN74SSTU32864 数据资料 dataSheet 下载.PDF
2. TI 德州仪器特殊逻辑产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)