SN74SSTL16847 具有三态输出的 20 位 SSTL_3 接口缓冲器

This 20-bit buffer is designed for 3-V to 3.6-V VCC operation and SSTL_3 input levels.

Data flow from A to Y is controlled by the output-enable (OE\). When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74SSTL16847 is characterized for operation from 0°C to 70°C

	SN74SSTL16847
Voltage Nodes(V)	3.3, 2.5
Technology Family	SSTL
Rating	Catalog

SN74SSTL16847 特性

• Member of the Texas Instruments WidebusTM Family
• Supports SSTL_3 Signal Inputs and Outputs
• Flow-Through Architecture Optimizes PCB Layout
• Meets SSTL_3 Class I and Class II Specifications
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• Packaged in Plastic Thin Shrink Small-Outline Package

SN74SSTL16847 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
74SSTL16847DGGRE4	ACTIVE	0 to 70	8.25 | 1ku	TSSOP (DGG) | 48	2000 | LARGE T&R
74SSTL16847DGGRG4	ACTIVE	0 to 70	8.25 | 1ku	TSSOP (DGG) | 48	2000 | LARGE T&R
SN74SSTL16847DGGR	ACTIVE	0 to 70	8.25 | 1ku	TSSOP (DGG) | 48	2000 | LARGE T&R

SN74SSTL16847 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
74SSTL16847DGGRE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74SSTL16847DGGRE4	74SSTL16847DGGRE4
74SSTL16847DGGRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74SSTL16847DGGRG4	74SSTL16847DGGRG4
SN74SSTL16847DGGR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74SSTL16847DGGR	SN74SSTL16847DGGR

SN74SSTL16847 应用技术支持与电子电路设计开发资源下载

1. SN74SSTL16847 数据资料 dataSheet 下载.PDF
2. TI 德州仪器特殊逻辑产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)