SN74S1051 12 位肖特基屏障二极管总线端接阵列

This Schottky barrier diode bus-termination array is designed to reduce reflection noise on memory bus lines. This device consists of a 12-bit high-speed Schottky diode array suitable for clamping to VCC and/or GND.

	SN74S1051
Voltage Nodes(V)	5
No. of Bits	12
Vf(Max)(V)	0.95
Vf (max)(V)	0.95
trr(max)(ns)	16
Technology Family	S

SN74S1051 特性

• Designed to Reduce Reflection Noise
• Repetitive Peak Forward Current to 200 mA
• 12-Bit Array Structure Suited for Bus-Oriented Systems

SN74S1051 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74S1051D	ACTIVE	0 to 70	5.10 | 1ku	SOIC (DW) | 16	25 | TUBE
SN74S1051DE4	ACTIVE	0 to 70	5.10 | 1ku	SOIC (DW) | 16	25 | TUBE
SN74S1051DG4	ACTIVE	0 to 70	5.10 | 1ku	SOIC (DW) | 16	25 | TUBE

SN74S1051 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74S1051D	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74S1051D	SN74S1051D
SN74S1051DE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74S1051DE4	SN74S1051DE4
SN74S1051DG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74S1051DG4	SN74S1051DG4

SN74S1051 应用技术支持与电子电路设计开发资源下载

1. SN74S1051 数据资料 dataSheet 下载.PDF
2. TI 德州仪器特殊逻辑产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)