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SN74S1050 12 位肖特基屏障二极管总线端接阵列

This Schottky barrier diode bus-termination array is designed to reduce reflection noise on memory bus lines. This devcie consists of a 12-bit high-speed Schottky diode array suitable for a clamp to GND.

The SN74S1050 is characterized for operation from 0°c to 70°C

SN74S1050
Voltage Nodes(V) 5
No. of Bits 12
Vf(Max)(V) 0.95
Vf (max)(V) 0.95
trr(max)(ns) 16
Technology Family S
SN74S1050 特性
SN74S1050 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74S1050D ACTIVE 0 to 70 5.10 | 1ku SOIC (DW) | 16 25 | TUBE  
SN74S1050DE4 ACTIVE 0 to 70 5.10 | 1ku SOIC (DW) | 16 25 | TUBE  
SN74S1050DG4 ACTIVE 0 to 70 5.10 | 1ku SOIC (DW) | 16 25 | TUBE  
SN74S1050 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74S1050D Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74S1050D SN74S1050D
SN74S1050DE4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74S1050DE4 SN74S1050DE4
SN74S1050DG4 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74S1050DG4 SN74S1050DG4
SN74S1050 应用技术支持与电子电路设计开发资源下载
  1. SN74S1050 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器特殊逻辑产品选型与价格 . xls
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  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
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