SN74LVTH18511 具有边界扫描的 3.3V ABT 18BIT 通用总线收发器
The SN74LVTH18511 is an 18-bit universal bus transceiver with boundary scan. This device supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, this device is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
In the normal mode, this device is an 18-bit UBT that combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. It can be used either as two 9-bit transceivers or one 18-bit transceiver. Activating the TAP in the normal mode does not affect the functional operation of the UBT
|
SN74LVTH18511 |
| Voltage Nodes(V) |
3.3, 2.7 |
| Vcc range(V) |
2.7 to 3.6 |
| Input Level |
TTL/CMOS |
| Output Level |
LVTTL |
| Output Drive(mA) |
-32/32 |
| No. of Bits |
18 |
| No. of Outputs |
19 |
| Logic |
True |
| Static Current |
24 |
| tpd max(ns) |
4.9 |
| Rating |
Catalog |
| Technology Family |
LVT |
SN74LVTH18511 特性
- Member of the Texas Instruments WidebusTM Family
- UBTTM Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
- State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Supports Unregulated Battery Operation Down to 2.7 V
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Compatible With the IEEE Std 1149.1-1990 (JTAG) Test Access Port and Boundary Scan Architecture
- IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP, HIGHZ, IDCODE
SN74LVTH18511 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| 74LVTH18511DGGRG4 |
ACTIVE |
-40 to 85 |
7.26 | 1ku |
TSSOP (DGG) | 64 |
2000 | LARGE T&R |
|
| SN74LVTH18511DGGR |
ACTIVE |
-40 to 85 |
7.26 | 1ku |
TSSOP (DGG) | 64 |
2000 | LARGE T&R |
|
SN74LVTH18511 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| 74LVTH18511DGGRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
74LVTH18511DGGRG4 |
74LVTH18511DGGRG4 |
| SN74LVTH18511PM |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74LVTH18511PM |
SN74LVTH18511PM |
SN74LVTH18511 应用技术支持与电子电路设计开发资源下载
- SN74LVTH18511 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)