SN74LVTH182502A 具有 18 位通用总线收发器的 3.3V ABT 扫描测试设备

The ’LVTH18502A and ’LVTH182502A scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 18-bit universal bus transceivers, that combine with D-type latches and D-type flip-flops, they allow data to flow in the transparent, latched, or clocked modes

	SN74LVTH182502A
Voltage Nodes(V)	3.3, 2.7
Vcc range(V)	2.7 to 3.6
Input Level	TTL/CMOS
Logic	True
No. of Outputs	18
Output Drive(mA)	-32/64
tpd max(ns)	5.7
Output Level	LVTTL
Static Current	13
Rating	Catalog
Technology Family	LVT

SN74LVTH182502A 特性

Members of the Texas Instruments SCOPETM Family of Testability Products
Members of the Texas Instruments WidebusTM Family
State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation Down to 2.7 V
UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors
B-Port Outputs of ’LVTH182502A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
SCOPETM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
- Parallel-Signature Analysis at Inputs
- Pseudorandom Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Device Identification
- Even-Parity Opcodes
Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

SN74LVTH182502A 芯片订购指南

器件	状态	温度	价格（美元）	封装 \| 引脚	封装数量 \| 封装载体	丝印标记
74LVTH182502APMG4	ACTIVE	-40 to 85	9.60 \| 1ku	LQFP (PM) \| 64	160 \| JEDEC TRAY (10+1)
74LVTH182502APMRG4	ACTIVE	-40 to 85	8.00 \| 1ku	LQFP (PM) \| 64	1000 \| LARGE T&R
SN74LVTH182502APM	ACTIVE	-40 to 85	9.60 \| 1ku	LQFP (PM) \| 64	160 \| JEDEC TRAY (10+1)
SN74LVTH182502APMR	ACTIVE	-40 to 85	8.00 \| 1ku	LQFP (PM) \| 64	1000 \| LARGE T&R

SN74LVTH182502A 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
74LVTH182502APMG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-3-260C-168 HR	74LVTH182502APMG4	74LVTH182502APMG4
74LVTH182502APMRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-3-260C-168 HR	74LVTH182502APMRG4	74LVTH182502APMRG4
SN74LVTH182502APM	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-3-260C-168 HR	SN74LVTH182502APM	SN74LVTH182502APM
SN74LVTH182502APMR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-3-260C-168 HR	SN74LVTH182502APMR	SN74LVTH182502APMR

SN74LVTH182502A 应用技术支持与电子电路设计开发资源下载

SN74LVTH182502A 数据资料 dataSheet 下载.PDF
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