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SN74LVTH16374-EP 具有三态输出的增强型产品 3.3V Abt 16 位边沿 D 类触发器

The SN74LVTH16374 is a 16-bit edge-triggered D-type flip-flop with 3-state outputs designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

This device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly

SN74LVTH16374-EP
Voltage Nodes(V) 3.3, 2.7
Technology Family LVT
Rating HiRel Enhanced Product
SN74LVTH16374-EP 特性
SN74LVTH16374-EP 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
CLVTH16374IDGGREP ACTIVE -40 to 85 1.69 | 1ku TSSOP (DGG) | 48 2000 | LARGE T&R  
CLVTH16374IDLREP ACTIVE -40 to 85 1.13 | 1ku SSOP (DL) | 48 1000 | LARGE T&R  
V62/04711-01XE ACTIVE -40 to 85 1.69 | 1ku TSSOP (DGG) | 48 2000 | LARGE T&R  
V62/04711-01YE ACTIVE -40 to 85 1.13 | 1ku SSOP (DL) | 48 1000 | LARGE T&R  
SN74LVTH16374-EP 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
CLVTH16374IDGGREP Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CLVTH16374IDGGREP CLVTH16374IDGGREP
CLVTH16374IDLREP Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CLVTH16374IDLREP CLVTH16374IDLREP
V62/04711-01XE Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04711-01XE V62/04711-01XE
V62/04711-01YE Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM V62/04711-01YE V62/04711-01YE
SN74LVTH16374-EP 应用技术支持与电子电路设计开发资源下载
  1. SN74LVTH16374-EP 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)