SN74LVTH162374 具有三态输出的 3.3V ABT 16 位边沿 D 类触发器

The 'LVTH162374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the Q outputs of the flip-flop take on the logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- series resistors to reduce overshoot and undershoot.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict

	SN74LVTH162374
Voltage Nodes(V)	3.3, 2.7
Technology Family	LVT
Rating	Catalog

SN74LVTH162374 特性

• Members of the Texas Instruments WidebusTMFamily
• Output Ports Have Equivalent 22- Series Resistors, So No External Resistors Are Required
• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
• Support Unregulated Battery Operation Down to 2.7 V
• Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
• Ioff and Power-Up 3-State Support Hot Insertion
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Distributed VCC and GND Pins Minimize High-Speed Switching Noise
• Flow-Through Architecture Optimizes PCB Layout
• Latch-Up Performance Exceeds 500 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)

SN74LVTH162374 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
74LVTH162374DGGRG4	ACTIVE	-40 to 85	1.00 | 1ku	TSSOP (DGG) | 48	2000 | LARGE T&R
74LVTH162374DLG4	ACTIVE	-40 to 85	1.30 | 1ku	SSOP (DL) | 48	25 | TUBE
74LVTH162374DLRG4	ACTIVE	-40 to 85	1.10 | 1ku	SSOP (DL) | 48	1000 | LARGE T&R
74LVTH162374GRDR	ACTIVE	-40 to 85	1.45 | 1ku	BGA MICROSTAR JUNIOR (GRD) | 54	1000 | LARGE T&R
74LVTH162374ZQLR	ACTIVE	-40 to 85	1.45 | 1ku	BGA MICROSTAR JUNIOR (ZQL) | 56	1000 | LARGE T&R
74LVTH162374ZRDR	ACTIVE	-40 to 85	1.45 | 1ku	BGA MICROSTAR JUNIOR (ZRD) | 54	1000 | LARGE T&R
SN74LVTH162374DGGR	ACTIVE	-40 to 85	1.00 | 1ku	TSSOP (DGG) | 48	2000 | LARGE T&R
SN74LVTH162374DL	ACTIVE	-40 to 85	1.30 | 1ku	SSOP (DL) | 48	25 | TUBE
SN74LVTH162374DLR	ACTIVE	-40 to 85	1.10 | 1ku	SSOP (DL) | 48	1000 | LARGE T&R
SN74LVTH162374KR	NRND	-40 to 85	1.45 | 1ku	BGA MICROSTAR JUNIOR (GQL) | 56	1000 | LARGE T&R

SN74LVTH162374 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
74LVTH162374DGGRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74LVTH162374DGGRG4	74LVTH162374DGGRG4
74LVTH162374DLG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74LVTH162374DLG4	74LVTH162374DLG4
74LVTH162374DLRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74LVTH162374DLRG4	74LVTH162374DLRG4
74LVTH162374GRDR	TBD	SNPB	Level-1-240C-UNLIM	74LVTH162374GRDR	74LVTH162374GRDR
74LVTH162374ZQLR	Green (RoHS & no Sb/Br)	SNAGCU	Level-1-260C-UNLIM	74LVTH162374ZQLR	74LVTH162374ZQLR
74LVTH162374ZRDR	Green (RoHS & no Sb/Br)	SNAGCU	Level-1-260C-UNLIM	74LVTH162374ZRDR	74LVTH162374ZRDR
SN74LVTH162374DGGR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LVTH162374DGGR	SN74LVTH162374DGGR
SN74LVTH162374DL	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LVTH162374DL	SN74LVTH162374DL
SN74LVTH162374DLR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LVTH162374DLR	SN74LVTH162374DLR
SN74LVTH162374KR	TBD	SNPB	Level-1-240C-UNLIM	SN74LVTH162374KR	SN74LVTH162374KR

SN74LVTH162374 应用技术支持与电子电路设计开发资源下载

1. SN74LVTH162374 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)