SN74LVT8980A 具有 8 位通用主机接口的嵌入式测试总线控制器 IEEE STD 1149.1 (JTAG) TAP 主控方

The ’LVT8980A embedded test-bus controllers (eTBCs) are members of the TI broad family of testability integrated circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most other devices of this family, the eTBCs are not boundary-scannable devices; rather, their function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command of an embedded host microprocessor/microcontroller. Thus, the eTBCs enable the practical and effective use of the IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and configuration/maintenance facilities at board and system levels.

The eTBCs master all TAP signals required to support one 4- or 5-wire IEEE Std 1149

	SN74LVT8980A
Voltage Nodes(V)	3.3, 2.7
Vcc range(V)	2.7 to 3.6
Input Level	TTL/CMOS
Output Level	LVTTL
No. of Bits	8
No. of Outputs	5
Output Drive(Max)(mA)	-32/64
Static Current(Max)(mA)	7
tpd max(ns)	30
Rating	Catalog
Technology Family	JTAG

SN74LVT8980A 特性

• Members of Texas Instruments Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture
• Provide Built-In Access to IEEE Std 1149.1 Scan-Accessible Test/Maintenance Facilities at Board and System Levels
• While Powered at 3.3 V, the TAP Interface Is Fully 5-V Tolerant for Mastering Both 5-V and/or 3.3-V IEEE Std 1149.1 Targets
• Simple Interface to Low-Cost 3.3-V Microprocessors/Microcontrollers Via 8-Bit Asynchronous Read/Write Data Bus
• Easy Programming Via Scan-Level Command Set and Smart TAP Control
• Transparently Generate Protocols to Support Multidrop TAP Configurations Using TI’s Addressable Scan Port
• Flexible TCK Generator Provides Programmable Division, Gated-TCK, and Free-Running-TCK Modes
• Discrete TAP Control Mode Supports Arbitrary TMS/TDI Sequences for Noncompliant Targets
• Programmable 32-Bit Test Cycle Counter Allows Virtually Unlimited Scan/Test Length
• Accommodate Target Retiming (Pipeline) Delays of up to 15 TCK Cycles
• Test Output Enable (TOE)\ Allows for External Control of TAP Signals
• High-Drive Outputs (–32-mA IOH, 64-mA IOL) at TAP Support Backplane Interface and/or High Fanout

SN74LVT8980A 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74LVT8980ADW	ACTIVE	-40 to 85	7.15 | 1ku	SOIC(DW) | 24	25 | TUBE
SN74LVT8980ADWR	ACTIVE	-40 to 85	7.15 | 1ku	SOIC(DW) | 24	2000 | LARGE T&R

SN74LVT8980A 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74LVT8980ADW	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LVT8980ADW	SN74LVT8980ADW
SN74LVT8980ADWR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LVT8980ADWR	SN74LVT8980ADWR

SN74LVT8980A 应用技术支持与电子电路设计开发资源下载

1. SN74LVT8980A 数据资料 dataSheet 下载.PDF
2. TI 德州仪器特殊逻辑产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)