SN74LVT18512 具有 18 位通用总线收发器的 3.3V ABT 扫描测试设备
The 'LVT18512 and 'LVT182512 scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes
|
SN74LVT18512 |
| Voltage Nodes(V) |
3.3, 2.7 |
| Vcc range(V) |
2.7 to 3.6 |
| Input Level |
TTL/CMOS |
| Logic |
True |
| No. of Outputs |
18 |
| Output Drive(mA) |
-32/64 |
| tpd max(ns) |
5.7 |
| Output Level |
LVTTL |
| Static Current |
16.5 |
| Rating |
Catalog |
| Technology Family |
LVT |
SN74LVT18512 特性
- Members of the Texas Instruments SCOPETM Family of Testability Products
- Members of the Texas Instruments WidebusTM Family
- State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Support Unregulated Battery Operation Down to 2.7 V
- UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
- B-Port Outputs of 'LVT182512 Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
- Compatible With the IEEE Std 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
- SCOPETM Instruction Set
- IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
- Parallel-Signature Analysis at Inputs
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Device Identification
- Even-Parity Opcodes
- Package Options Include 64-Pin Plastic Thin Shrink Small Outline (DGG) and 64-Pin Ceramic Dual Flat (HKC) Packages Using 0.5-mm Center-to-Center Spacings
SN74LVT18512 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| 74LVT18512DGGRE4 |
ACTIVE |
-40 to 85 |
6.60 | 1ku |
TSSOP (DGG) | 64 |
2000 | LARGE T&R |
|
| 74LVT18512DGGRG4 |
ACTIVE |
-40 to 85 |
6.60 | 1ku |
TSSOP (DGG) | 64 |
2000 | LARGE T&R |
|
| SN74LVT18512DGGR |
ACTIVE |
-40 to 85 |
6.60 | 1ku |
TSSOP (DGG) | 64 |
2000 | LARGE T&R |
|
SN74LVT18512 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| 74LVT18512DGGRE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
74LVT18512DGGRE4 |
74LVT18512DGGRE4 |
| 74LVT18512DGGRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
74LVT18512DGGRG4 |
74LVT18512DGGRG4 |
| SN74LVT18512DGGR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74LVT18512DGGR |
SN74LVT18512DGGR |
SN74LVT18512 应用技术支持与电子电路设计开发资源下载
- SN74LVT18512 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)