SN74LVCH32373A 具有三态输出的 32 位透明 D 类锁存器
This 32-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVCH32373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly
|
SN74LVCH32373A |
| Voltage Nodes(V) |
3.3, 2.7, 2.5, 1.8 |
| Vcc range(V) |
1.65 to 3.6 |
| Input Level |
TTL/CMOS |
| Output Level |
LVTTL |
| Logic |
True |
| No. of Bits |
32 |
| No. of Outputs |
32 |
| Output Drive(mA) |
-24/24 |
| Static Current |
0.04 |
| th(ns) |
1.2 |
| Technology Family |
LVC |
| tsu(ns) |
1.7 |
| tpd max(ns) |
4.9 |
| Rating |
Catalog |
|
SN74LVCH32373A |
| Voltage Nodes(V) |
3.3, 2.7, 2.5, 1.8 |
| Vcc range(V) |
1.65 to 3.6 |
| Input Level |
TTL/CMOS |
| Output Level |
LVTTL |
| Logic |
True |
| No. of Bits |
32 |
| No. of Outputs |
32 |
| Output Drive(mA) |
-24/24 |
| Static Current |
0.04 |
| th(ns) |
1.2 |
| Technology Family |
LVC |
| tsu(ns) |
1.7 |
| tpd max(ns) |
4.9 |
| Rating |
Catalog |
SN74LVCH32373A 特性
- Memeber of the Texas Instruments Widebus+TM Family
- Operate From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.2 ns at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA= 25°C
- Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
- Ioff Supports Partial-Power-Down Mode Operation
- Supports Mixed-Mode Signal Operation on All Ports (5-V Input and Output Voltages With 3.3-V VCC)
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
SN74LVCH32373A 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN74LVCH32373AGKER |
NRND |
-40 to 85 |
12.10 | 1ku |
LFBGA (GKE) | 96 |
1000 | LARGE T&R |
|
| SN74LVCH32373AZKER |
ACTIVE |
-40 to 85 |
5.75 | 1ku |
LFBGA (ZKE) | 96 |
1000 | LARGE T&R |
|
SN74LVCH32373A 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN74LVCH32373AGKER |
TBD |
SNPB |
Level-2-235C-1 YEAR |
SN74LVCH32373AGKER |
SN74LVCH32373AGKER |
| SN74LVCH32373AZKER |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
SN74LVCH32373AZKER |
SN74LVCH32373AZKER |
SN74LVCH32373A 应用技术支持与电子电路设计开发资源下载
- SN74LVCH32373A 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)