SN74LVCH16901 具有奇偶校验发生器/校验器的 18 位通用总线收发器
This 18-bit (dual-octal) noninverting registered transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver, or it can generate/check parity from the two 8-bit data buses in either direction.
The SN74LVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB\ or CLKENBA\) inputs. It also provides parity-enable (SEL)\ and parity-select (ODD/EVEN\) inputs and separate error-signal (ERRA\ or ERRB\) outputs for checking parity. The direction of data flow is controlled by output-enable (OEAB\ and OEBA\) inputs. When SEL\ is low, the parity functions are enabled
|
SN74LVCH16901 |
| Voltage Nodes(V) |
3.3, 2.7, 2.5, 1.8 |
| Rating |
Catalog |
| Technology Family |
LVC |
SN74LVCH16901 特性
- Member of the Texas Instruments Widebus+TM Family
- UBTTM Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
- Operates From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 5.4 ns at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
- Simultaneously Generates and Checks Parity
- Option to Select Generate Parity and Check or Feed-Through Data/Parity in A-to-B or B-to-A Direction
- Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
- Ioff Supports Partial-Power-Down Mode Operation
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class I
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
SN74LVCH16901 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| 74LVCH16901DGGRE4 |
ACTIVE |
-40 to 85 |
8.25 | 1ku |
TSSOP (DGG) | 64 |
2000 | LARGE T&R |
|
| 74LVCH16901DGGRG4 |
ACTIVE |
-40 to 85 |
8.25 | 1ku |
TSSOP (DGG) | 64 |
2000 | LARGE T&R |
|
| SN74LVCH16901DGGR |
ACTIVE |
-40 to 85 |
8.25 | 1ku |
TSSOP (DGG) | 64 |
2000 | LARGE T&R |
|
SN74LVCH16901 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| 74LVCH16901DGGRE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
74LVCH16901DGGRE4 |
74LVCH16901DGGRE4 |
| 74LVCH16901DGGRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
74LVCH16901DGGRG4 |
74LVCH16901DGGRG4 |
| SN74LVCH16901DGGR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74LVCH16901DGGR |
SN74LVCH16901DGGR |
SN74LVCH16901 应用技术支持与电子电路设计开发资源下载
- SN74LVCH16901 数据资料 dataSheet 下载.PDF
- TI 德州仪器通用总线功能产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)