SN74LVC573A-EP 具有三态输出的增强型产品八路 D 类透明锁存器

The SN74LVC573A-EP octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation.

This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly

	SN74LVC573A-EP
Voltage Nodes(V)	3.3, 2.7
Vcc range(V)	2.0 to 3.6
Input Level	TTL/CMOS
Output Level	LVTTL
Logic	True
No. of Bits
No. of Outputs	8
Output Drive(mA)	-24/24
Static Current	0.01
th(ns)	2.5
Technology Family	LVC
tsu(ns)	2
tpd max(ns)	7.7
Rating	HiRel Enhanced Product

SN74LVC573A-EP 特性

• Controlled Baseline
  • One Assembly/Test Site, One Fabrication Site
• Extended Temperature Performance of –40°C to 125°C
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree
• Operates From 2 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max tpd of 6.9 ns at 3.3 V
• Typical VOLP (Output Ground Bounce)
  <0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
  >2 V at VCC = 3.3 V, TA = 25°C
• Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
• Ioff Supports Partial-Power-Down Mode Operation

SN74LVC573A-EP 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74LVC573AMDBREP	ACTIVE	-55 to 125	0.79 | 1ku	SSOP (DB) | 20	2000 | LARGE T&R
SN74LVC573AQDWREP	ACTIVE	-40 to 125	0.45 | 1ku	SOIC (DW) | 20	2000 | LARGE T&R
SN74LVC573AQPWREP	ACTIVE	-40 to 125	0.45 | 1ku	TSSOP (PW) | 20	2000 | LARGE T&R
V62/04667-01XE	ACTIVE	-40 to 125	0.45 | 1ku	SOIC (DW) | 20	2000 | LARGE T&R
V62/04667-01YE	ACTIVE	-40 to 125	0.45 | 1ku	TSSOP (PW) | 20	2000 | LARGE T&R
V62/04662-02ZE	ACTIVE	-55 to 125	0.79 | 1ku	SSOP (DB) | 20	2000 | LARGE T&R

SN74LVC573A-EP 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74LVC573AMDBREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LVC573AMDBREP	SN74LVC573AMDBREP
SN74LVC573AQDWREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LVC573AQDWREP	SN74LVC573AQDWREP
SN74LVC573AQPWREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LVC573AQPWREP	SN74LVC573AQPWREP
V62/04667-01XE	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	V62/04667-01XE	V62/04667-01XE
V62/04667-01YE	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	V62/04667-01YE	V62/04667-01YE
V62/04662-02ZE	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	V62/04662-02ZE	V62/04662-02ZE

SN74LVC573A-EP 应用技术支持与电子电路设计开发资源下载

1. SN74LVC573A-EP 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)