This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down
SN74LVC1G79-EP | |
Pin/Package | 5SC70 |
Operating Temperature Range(°C) | -55 to 115 |
Technology Family | LVC |
Rating | HiRel Enhanced Product |
器件 | 状态 | 温度 | 价格(美元) | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN74LVC1G79WDCKREP | ACTIVE | -55 to 115 | 0.28 | 1ku | SC70 (DCK) | 5 | 3000 | LARGE T&R | |
V62/05621-01XE | ACTIVE | -55 to 115 | 0.28 | 1ku | SC70 (DCK) | 5 | 3000 | LARGE T&R |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN74LVC1G79WDCKREP | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC1G79WDCKREP | SN74LVC1G79WDCKREP |
V62/05621-01XE | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | V62/05621-01XE | V62/05621-01XE |