SN74LVC1G04-EP 增强型产品单路反向器闸

This single inverter gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G04 performs the Boolean function Y = A.

NanoStarTM and NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down

	SN74LVC1G04-EP
Pin/Package	5SOT-23
Operating Temperature Range(°C)	-55 to 125
Vcc max(V)	5.5
Technology Family	LVC
Vcc min(V)	1.65
No. of Gates	1
ICC(uA)	10
Rating	HiRel Enhanced Product

SN74LVC1G04-EP 特性

• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 3.3 ns at 3.3 V
• Low Power Consumption, 10-uA Max ICC
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)
• SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
  • Controlled Baseline
  • One Assembly/Test Site
  • One Fabrication Site
  • Available in Military (–55°C/125°C) Temperature Range(1)
  • Extended Product Life Cycle
  • Extended Product-Change Notification
  • Product Traceability

SN74LVC1G04-EP 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74LVC1G04MDBVREP	ACTIVE	-40 to 125	0.70 | 1ku	SOT-23 (DBV) | 5	3000 | LARGE T&R

SN74LVC1G04-EP 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74LVC1G04MDBVREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LVC1G04MDBVREP	SN74LVC1G04MDBVREP

SN74LVC1G04-EP 应用技术支持与电子电路设计开发资源下载

1. SN74LVC1G04-EP 数据资料 dataSheet 下载.PDF
2. TI 德州仪器小尺寸逻辑器件产品选型与价格 . xls
3. Logic Guide 2009 (PDF 4263 KB)
4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
9. Designing With Logic (PDF 186 KB)
10. Live Insertion (PDF 150 KB)
11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
14. LOGIC Pocket Data Book (PDF 6001 KB)
15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
16. Logic Cross-Reference (PDF 2938 KB)