SN74LVC16373A-EP 具有三态输出的增强型产品 16 位 D 类透明锁存器

This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC16373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down

	SN74LVC16373A-EP
Voltage Nodes(V)	3.3, 2.7, 2.5, 1.8
Rating	Catalog

SN74LVC16373A-EP 特性

• Member of the Texas Instruments WidebusTM Family
• Operates From 1.65 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max tpd of 4.2 ns at 3.3 V
• Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Partial-Power-Down Mode Operation
• Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 1000-V Charged-Device Model (C101)

SN74LVC16373A-EP 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
CLVC16373AMDLREP	ACTIVE	-55 to 125	2.66 | 1ku	SSOP (DL) | 48	1000 | LARGE T&R
V62/06649-01XE	ACTIVE	-55 to 125	2.66 | 1ku	SSOP (DL) | 48	1000 | LARGE T&R

SN74LVC16373A-EP 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
CLVC16373AMDLREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CLVC16373AMDLREP	CLVC16373AMDLREP
V62/06649-01XE	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	V62/06649-01XE	V62/06649-01XE

SN74LVC16373A-EP 应用技术支持与电子电路设计开发资源下载

1. SN74LVC16373A-EP 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)