SN74LVC157A-EP 增强型产品四路 2 线路至 1 线路数据选择器/多路复用器

The SN74LVC157A-EP quadruple 2-line to 1-line data selector/multiplexer is designed for 2.7-V to 3.6-V VCC operation.

This device features a common strobe (G)\ input. When G\ is high, all outputs are low. When G\ is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. The device provides true data.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment

	SN74LVC157A-EP
Rating	HiRel Enhanced Product
Technology Family	LVC

SN74LVC157A-EP 特性

• Controlled Baseline
  • One Assembly/Test Site, One Fabrication Site
• Extended Temperature Performance of –40°C to 125°C
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Operates From 2 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max tpd of 5.4 ns at 3.3 V
• Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C

SN74LVC157A-EP 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74LVC157AQDREP	ACTIVE	-40 to 125	0.41 | 1ku	SOIC (D) | 16	2500 | LARGE T&R
V62/04659-01XE	ACTIVE	-40 to 125	0.41 | 1ku	SOIC (D) | 16	2500 | LARGE T&R

SN74LVC157A-EP 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74LVC157AQDREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LVC157AQDREP	SN74LVC157AQDREP
V62/04659-01XE	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	V62/04659-01XE	V62/04659-01XE

SN74LVC157A-EP 应用技术支持与电子电路设计开发资源下载

1. SN74LVC157A-EP 数据资料 dataSheet 下载.PDF
2. TI 德州仪器MSI 功能产品选型与价格 . xls
3. Logic Guide 2009 (PDF 4263 KB)
4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
9. Designing With Logic (PDF 186 KB)
10. Live Insertion (PDF 150 KB)
11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
14. LOGIC Pocket Data Book (PDF 6001 KB)
15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
16. Logic Cross-Reference (PDF 2938 KB)