SN74LV221A 双路单稳多频振荡器
The ’LV221A devices are dual multivibrators designed for 2-V to 5.5-V VCC operation. Each multivibrator has a negative-transition-triggered (A\) input and a positive-transition-triggered (B) input, either of which can be used as an inhibit input.
These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A\ input is low and the B input goes high. In the second method, the B input is high and the A\ input goes low. In the third method, the A\ input is low, the B input is high, and the clear (CLR\) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC
| SN74LV221A | |
| Voltage Nodes(V) | 5, 3.3, 2.5 |
| Vcc range(V) | 2 to 5.5 |
| Rating | Catalog |
| Technology Family | LV-A |
SN74LV221A 特性
- 2-V to 5.5-V VCC Operation
- Max tpd of 11 ns at 5 V
- Support Mixed-Mode Voltage Operation on All Ports
- Schmitt-Trigger Circuitry on A\, B, and CLR\ Inputs for Slow Input Transition Rates
- Overriding Clear Terminates Output Pulse
- Glitch-Free Power-Up Reset on Outputs
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74LV221A 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LV221AD | ACTIVE | 0 to 70 | 3.00 | 1ku | SOIC (D) | 16 | 50 | TUBE | |
| SN74LV221ADE4 | ACTIVE | 0 to 70 | 3.00 | 1ku | SOIC (D) | 16 | 50 | TUBE | |
| SN74LV221ADG4 | ACTIVE | 0 to 70 | 3.00 | 1ku | SOIC (D) | 16 | 50 | TUBE | |
| SN74LV221ADR | ACTIVE | 0 to 70 | 2.50 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | |
| SN74LV221ADRE4 | ACTIVE | 0 to 70 | 2.50 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | |
| SN74LV221ADRG4 | ACTIVE | 0 to 70 | 2.50 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | |
| SN74LV221AN | ACTIVE | 0 to 70 | 2.75 | 1ku | PDIP (N) | 16 | 25 | TUBE | |
| SN74LV221ANE4 | ACTIVE | 0 to 70 | 2.75 | 1ku | PDIP (N) | 16 | 25 | TUBE |
SN74LV221A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LV221AD | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV221AD | SN74LV221AD |
| SN74LV221ADE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV221ADE4 | SN74LV221ADE4 |
| SN74LV221ADG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV221ADG4 | SN74LV221ADG4 |
| SN74LV221ADR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV221ADR | SN74LV221ADR |
| SN74LV221ADRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV221ADRE4 | SN74LV221ADRE4 |
| SN74LV221ADRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV221ADRG4 | SN74LV221ADRG4 |
| SN74LV221AN | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LV221AN | SN74LV221AN |
| SN74LV221ANE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LV221ANE4 | SN74LV221ANE4 |
SN74LV221A 应用技术支持与电子电路设计开发资源下载
- SN74LV221A 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)