SN74LS75 四路双稳态锁存器
These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (C) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go high.
The '75 and 'LS75 feature complementary Q and Q\ outputs from a 4-bit latch, and are available in various 16-pin packages. For higher component density applications, the '77 and 'LS77 4-bit latches are available in 14-pin flat packages
| SN74LS75 | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.75 to 5.25 |
| Input Level | TTL |
| Output Level | TTL |
| Output Drive(mA) | -0.4/8 |
| Output | 2S |
| No. of Bits | 4 |
| th(ns) | 5 |
| tpd max(ns) | 19 |
| tsu(ns) | 20 |
| Rating | Catalog |
| Technology Family | LS |
SN74LS75 特性
- Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout
SN74LS75 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LS75D | ACTIVE | 0 to 70 | 2.70 | 1ku | SOIC (D) | 16 | 40 | TUBE | LS75 |
| SN74LS75DE4 | ACTIVE | 0 to 70 | 2.70 | 1ku | SOIC (D) | 16 | 40 | TUBE | LS75 |
| SN74LS75DG4 | ACTIVE | 0 to 70 | 2.70 | 1ku | SOIC (D) | 16 | 40 | TUBE | LS75 |
| SN74LS75DR | ACTIVE | 0 to 70 | 2.25 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | LS75 |
| SN74LS75DRE4 | ACTIVE | 0 to 70 | 2.25 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | LS75 |
| SN74LS75DRG4 | ACTIVE | 0 to 70 | 2.25 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | LS75 |
| SN74LS75N | ACTIVE | 0 to 70 | 2.45 | 1ku | PDIP (N) | 16 | 25 | TUBE | SN74LS75N |
| SN74LS75NE4 | ACTIVE | 0 to 70 | 2.45 | 1ku | PDIP (N) | 16 | 25 | TUBE | SN74LS75N |
SN74LS75 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LS75D | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS75D | SN74LS75D |
| SN74LS75DE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS75DE4 | SN74LS75DE4 |
| SN74LS75DG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS75DG4 | SN74LS75DG4 |
| SN74LS75DR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS75DR | SN74LS75DR |
| SN74LS75DRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS75DRE4 | SN74LS75DRE4 |
| SN74LS75DRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS75DRG4 | SN74LS75DRG4 |
| SN74LS75N | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LS75N | SN74LS75N |
| SN74LS75NE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LS75NE4 | SN74LS75NE4 |
SN74LS75 应用技术支持与电子电路设计开发资源下载
- SN74LS75 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)