SN74LS73A 具有清零功能的双路 J-K 触发器
The '73, and 'H73, contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '73, and 'H73, are positive pulse-triggered flip-flops. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.
The 'LS73A contains two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.
The SN5473, SN54H73, and the SN54LS73A are characterized for operation over the full military temperature range of -55°C to 125°C
| SN74LS73A | |
| Voltage Nodes(V) | 5 |
| Technology Family | LS |
| Rating | Catalog |
SN74LS73A 特性
- Package Options Include Plastic “Small Outline" Packages, Flat Packages, and Plastic and Ceramic DIPs
- Dependable Texas Instruments Quality and Reliability
SN74LS73A 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LS73AD | ACTIVE | 0 to 70 | 1.40 | 1ku | SOIC (D) | 14 | 50 | TUBE | LS73 |
| SN74LS73ADE4 | ACTIVE | 0 to 70 | 1.40 | 1ku | SOIC (D) | 14 | 50 | TUBE | LS73 |
| SN74LS73ADG4 | ACTIVE | 0 to 70 | 1.40 | 1ku | SOIC (D) | 14 | 50 | TUBE | LS73 |
| SN74LS73ADR | ACTIVE | 0 to 70 | 1.20 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | SN74LS73AN |
| SN74LS73ADRE4 | ACTIVE | 0 to 70 | 1.20 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | SN74LS73AN |
| SN74LS73ADRG4 | ACTIVE | 0 to 70 | 1.20 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | LS73 |
| SN74LS73AN | ACTIVE | 0 to 70 | 1.30 | 1ku | PDIP (N) | 14 | 25 | TUBE | LS73 |
| SN74LS73ANE4 | ACTIVE | 0 to 70 | 1.30 | 1ku | PDIP (N) | 14 | 25 | TUBE | LS73 |
SN74LS73A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LS73AD | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS73AD | SN74LS73AD |
| SN74LS73ADE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS73ADE4 | SN74LS73ADE4 |
| SN74LS73ADG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS73ADG4 | SN74LS73ADG4 |
| SN74LS73ADR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS73ADR | SN74LS73ADR |
| SN74LS73ADRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS73ADRE4 | SN74LS73ADRE4 |
| SN74LS73ADRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS73ADRG4 | SN74LS73ADRG4 |
| SN74LS73AN | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LS73AN | SN74LS73AN |
| SN74LS73ANE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LS73ANE4 | SN74LS73ANE4 |
SN74LS73A 应用技术支持与电子电路设计开发资源下载
- SN74LS73A 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)