SN74LS107A 具有清零功能的双路 J-K 触发器

The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C

	SN74LS107A
Voltage Nodes(V)	5
Technology Family	HC
Rating	Catalog

SN74LS107A 特性

• Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability

SN74LS107A 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74LS107AD	ACTIVE	0 to 70	1.40 | 1ku	SOIC (D) | 14	50 | TUBE	LS107A
SN74LS107ADE4	ACTIVE	0 to 70	1.40 | 1ku	SOIC (D) | 14	50 | TUBE	LS107A
SN74LS107ADG4	ACTIVE	0 to 70	1.40 | 1ku	SOIC (D) | 14	50 | TUBE	LS107A
SN74LS107ADR	ACTIVE	0 to 70	1.20 | 1ku	SOIC (D) | 14	2500 | LARGE T&R	LS107A
SN74LS107ADRE4	ACTIVE	0 to 70	1.20 | 1ku	SOIC (D) | 14	2500 | LARGE T&R	LS107A
SN74LS107ADRG4	ACTIVE	0 to 70	1.20 | 1ku	SOIC (D) | 14	2500 | LARGE T&R	LS107A
SN74LS107AN	ACTIVE	0 to 70	1.30 | 1ku	PDIP (N) | 14	25 | TUBE	SN74LS107AN
SN74LS107AN3	OBSOLETE	0 to 70		PDIP (N) | 14		SN74LS107AN
SN74LS107ANE4	ACTIVE	0 to 70	1.30 | 1ku	PDIP (N) | 14	25 | TUBE	SN74LS107AN
SN74LS107ANSR	ACTIVE	0 to 70	1.30 | 1ku	SO (NS) | 14	2000 | LARGE T&R	LS107A
SN74LS107ANSRE4	ACTIVE	0 to 70	1.30 | 1ku	SO (NS) | 14	2000 | LARGE T&R	LS107A
SN74LS107ANSRG4	ACTIVE	0 to 70	1.30 | 1ku	SO (NS) | 14	2000 | LARGE T&R	LS107A

SN74LS107A 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74LS107AD	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LS107AD	SN74LS107AD
SN74LS107ADE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LS107ADE4	SN74LS107ADE4
SN74LS107ADG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LS107ADG4	SN74LS107ADG4
SN74LS107ADR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LS107ADR	SN74LS107ADR
SN74LS107ADRE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LS107ADRE4	SN74LS107ADRE4
SN74LS107ADRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LS107ADRG4	SN74LS107ADRG4
SN74LS107AN	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	SN74LS107AN	SN74LS107AN
SN74LS107ANE4	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	SN74LS107ANE4	SN74LS107ANE4
SN74LS107ANSR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LS107ANSR	SN74LS107ANSR
SN74LS107ANSRE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LS107ANSRE4	SN74LS107ANSRE4
SN74LS107ANSRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LS107ANSRG4	SN74LS107ANSRG4

SN74LS107A 应用技术支持与电子电路设计开发资源下载

1. SN74LS107A 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)